Measurement Computing CIO-PDMAxx - Manual (Page 16)

RL1 to RL0 are the read and load control bits:
RL1 RL0 OPERATION
0 0 Latch counter.
0 1 Read/load high byte.
1 0 Read/load low byte.
1 1 Read/load low then high byte (word transfer).
M2 to M0 are the counter control operation type bits:
M2 M1 M0 OPERATION TYPE
0 0 0 Change on terminal count.
0 0 1 Programmable one-shot.
0 1 0 Rate generator
0 1 1 Square wave generator
1 0 0 Software triggered strobe.
1 0 1 Hardware triggered strobe.
BCD = 0 then counter data is 16-bit binary. (65,535 max)
BCD = 1 then counter data is 4-decade Binary-Coded-Decimal. (9,999 max)
Figure 5-1. Pacer Clock Block Diagram
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