BECKHOFF EL9800 Basisplatine - Manual (Page 15)

Product overview
EL9800 13
1 8/16 Bit µ-Controller Interface
2 32 Bit digital Interface - 32 Inputs
3 32 Bit digital Interface - 32 Outputs
4 32 Bit digital Interface - 16 Inputs / 16 Outputs
5 32 Bit digital Interface - 24 Inputs / 8 Outputs
6 32 Bit digital Interface - 8 Inputs / 24 Outputs
7 PIC (SPI)
8 SPI
All postage stamps indicate successful loading of the EtherCAT configuration from the EEPROM with an
LED in the EL9800 base board.
The EL9800 base board supports automatic differentiation between FPGA-based postage stamps and
ASIC (e.g. ET1100) based ones. Therefore the programming voltage on the connector J203 is detected
and evaluated. In case of a missing programming voltage the behaviour of the EL9800 base board can be
configured using the connector J1202. Figure 8 shows the pinout of the connector J1202.
+3.3V GND
FB-Detect
Figure 8 Pinout of the connector J1201
The delivery status of this connector is not bridged. FB-Detect has to be bridged to +3.3V, when FB1111-
140 and FB1111-141 postage stamps are used in combination with the EL9800 evaluation board. Pre-
condition for correct communication between EtherCAT postage stamp and EL9800 base board is the
correct configuration of the EtherCAT device. As well on the IP-Core based FPGA postage stamps as on
ET1100-ASIC based postage stamps the process data interface has to be configured by loading the spe-
cific binary file into the configuration EEPROM (*bin).