Artesyn COMX-P40x0 ENP2 Installation and Use (August 2014) - Manual (Page 96)

BSP
COMX-P40x0 ENP2 Installation and Use (6806800R95B) 96
When the U-Boot detects the DDR3 SDRAM during boot up, the following message appears:
7.11 GPIO
COMX-P40X0-ENP2 has 20 general purpose input/output (GPIO), 12 connected to the CPU,
and 8 implemented on an I2C expander. For more information, see
GPIO on page 68 .
For more information, see GPIO on page 68 .
DRAM: Initializing...
2 GB left unmapped
DDR: 4 GB (DDR3, 64-bit, CL=9, ECC on)
DDR Controller Interleving Mode: cache line
DDR Chip-Select Interleaving Mode: CS0+CS1
Table 7-4 GPIO States
GPIO# Input/Output Reset State Description
GPIO00 I I GPI0 of COM-E connectors
GPIO01 I I GPI1 of COM-E connectors
GPIO02 I I GPI3 of COM-E connectors
GPIO03 I I GPI4 of COM-E connectors
GPIO04 O I GPO0 of COM-E connectors and also as to control
debug LED D18
GPIO05 O I GPO1 of COM-E connectors and also as to control
debug LED D19
GPIO06 O I GPO3 of COM-E connectors
GPIO07 O I GPO4 of COM-E connectors
GPIO19 O I Clock Generator Enable
GPIO20 O I Carried board reset output
GPIO23 I I Clock generator of bank 1 frequency selection input
GPIO24 I I Clock generator of bank 2/3 frequency selection input