Artesyn COMX-P40x0 ENP2 Installation and Use (August 2014) - Manual (Page 61)

Functional Description
COMX-P40x0 ENP2 Installation and Use (6806800R95B) 61
4.5.1 Clock
The eLBC clock is generated by platform clock. The divisor is configured by CLKDIV in Clock
Ratio Register (LCRR). The clock is limited to 75MHz maximum frequency.
4.5.2 NOR FLASH
The NOR FLASH is attached to the GPCM on the local bus and operates in 16-bit mode.
The NOR FLASH is a Micron PC28F00BM29EWHA. Its size is 2Gb/ 256MB. It has 2048 uniform
blocks, 128K bytes or 64K words each.
The physical address for the NOR FLASH is 0xFE0000000 - 0xFEFFFFFFF.
The NOR FLASH contains RCW data, U-Boot image, U-Boot environment variables, kernel
image, device tree blob, RAMDISK image and FMAN ucode image. The detailed map is
described in the following table:
Table 4-1 NOR FLASH Map
Block# Blocks Start End Size Description
0 1 0000 0000 0001 FFFF 128 KB Active RCW Option
Data
1 1 0002 0000 0003 FFFF 128 KB RCW Option Data 1
2 1 0004 0000 0005 FFFF 128 KB RCW Option Data 2
3 1 0006 0000 0007 FFFF 128 KB RCW Option Data 3
4 1 0008 0000 0009 FFFF 128 KB RCW Option Data 4
5 1 000A 0000 000B FFFF 128 KB RCW Option Data 5
6 1 000C 0000 000D FFFF 128 KB RCW Option Data 6
7 1 000E 0000 000F FFFF 128 KB RCW Option Data 7
8 1 0010 0000 0011 FFFF 128 KB RCW Option Data 8
9 1 0012 0000 0013 FFFF 128 KB RCW Option Data 9
10 1 0014 0000 0015 FFFF 128 KB RCW Option Data 10
11 1 0016 0000 0017 FFFF 128 KB RCW Option Data 11
12 1 0018 0000 0019 FFFF 128 KB RCW Option Data 12