Altera Cyclone III Development Board - Manual (Page 62)

2–52 Chapter 2: Board Components
On-Board Memory
Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation
U25 pin F7 Data strobe 2 SSTL18 Class 1 DDR2_DQS2 AF11
U25 pin B7 Data strobe 3 SSTL18 Class 1 DDR2_DQS3 AE10
U11 pin F7 Data strobe 4 SSTL18 Class 1 DDR2_DQS4 D12
U11 pin B7 Data strobe 5 SSTL18 Class 1 DDR2_DQS5 E12
U12 pin F7 Data strobe 6 SSTL18 Class 1 DDR2_DQS6 B17
U12 pin B7 Data strobe 7 SSTL18 Class 1 DDR2_DQS7 D17
U13 pin B7 Data strobe 8 SSTL18 Class 1 DDR2_DQS8 A25
U25, U26 pin M8 Bottom address 0 SSTL18 Class 1 DDR2BOT_A0 AB22
U25, U26 pin M3 Bottom address 1 SSTL18 Class 1 DDR2BOT_A1 AG6
U25, U26 pin M2 Bottom address 10 SSTL18 Class 1 DDR2BOT_A10 AE4
U25, U26 pin P7 Bottom address 11 SSTL18 Class 1 DDR2BOT_A11 AF21
U25, U26 pin R2 Bottom address 12 SSTL18 Class 1 DDR2BOT_A12 Y12
U25, U26 pin R8 Bottom address 13 SSTL18 Class 1 DDR2BOT_A13 Y14
U25, U26 pin R3 Bottom address 14 SSTL18 Class 1 DDR2BOT_A14 AF12
U25, U26 pin R7 Bottom address 15 SSTL18 Class 1 DDR2BOT_A15 AA16
U25, U26 pin M7 Bottom address 2 SSTL18 Class 1 DDR2BOT_A2 Y13
U25, U26 pin N2 Bottom address 3 SSTL18 Class 1 DDR2BOT_A3 AE7
U25, U26 pin N8 Bottom address 4 SSTL18 Class 1 DDR2BOT_A4 AB12
U25, U26 pin N3 Bottom address 5 SSTL18 Class 1 DDR2BOT_A5 AC7
U25, U26 pin N7 Bottom address 6 SSTL18 Class 1 DDR2BOT_A6 AD12
U25, U26 pin P2 Bottom address 7 SSTL18 Class 1 DDR2BOT_A7 AB8
U25, U26 pin P8 Bottom address 8 SSTL18 Class 1 DDR2BOT_A8 AH12
U25, U26 pin P3 Bottom address 9 SSTL18 Class 1 DDR2BOT_A9 AB10
LED D16 pin 2 Bottom bus activity LED 1.8 V DDR2BOT_ACTIVE AA14
U25, U26 pin L2 Bottom bank address 0 SSTL18 Class 1 DDR2BOT_BA0 AF3
U25, U26 pin L3 Bottom bank address 1 SSTL18 Class 1 DDR2BOT_BA1 AF5
U25, U26 pin L1 Bottom bank address 2 SSTL18 Class 1 DDR2BOT_BA2 AH4
U25, U26 pin L7 Bottom column address
strobe SSTL-18 Class I DDR2BOT_CASn AD21
U25, U26 pin K2 Bottom clock enable SSTL-18 Class I DDR2BOT_CKE AG4
U25, U26 pin L8 Bottom chip select SSTL-18 Class I DDR2BOT_CSn AC21
U25, U26 pin K9 Bottom on-die
termination enable SSTL-18 Class I DDR2BOT_ODT AE24
U25, U26 pin K7 Bottom row address
strobe SSTL-18 Class I DDR2BOT_RASn AE21
U25, U26 pin K3 Bottom write enable SSTL-18 Class I DDR2BOT_WEn AE5
U11, U12 pin M8, U13 pin H8 Top address 0 SSTL18 Class 1 DDR2TOP_A0 J13
U11, U12 pin M3, U13 pin H3 Top address 1 SSTL18 Class 1 DDR2TOP_A1 G18
U11, U12 pin M2, U13 pin H2 Top address 10 SSTL18 Class 1 DDR2TOP_A10 A17
Table 2–51. DDR2 Interface I/O (Part 4 of 5)
Board
Reference Description I/O Standard
Schematic
Signal Name
Cyclone III
Device Pin
Number