Altera Cyclone III Development Board User Manual
Page 53
Chapter 2: Board Components
2–43
Communication Ports and Interfaces
© March 2009 Altera Corporation
Cyclone III 3C120 Development Board Reference Manual
1
As noted in the HSMC specification, LVDS and single-ended I/O standards are only
guaranteed to function when mixed according to either the generic single-ended
pin-out or the generic differential pin-out.
lists the HSMC Port A interface signal name, description, and I/O
standard. Signal name and direction are relative to the Cyc
lone III FPGA, which is the
HSMC host.
Table 2–47. HSMC Port A Interface Signal Name, Description, and Type (Part 1 of 3)
Board
Reference
Description
I/O Standard
Schematic
Signal Name
Cyclone III
Device Pin
Number
J8 pin 33
Management serial data
2.5 V
HSMA_SDA
AC1
J8 pin 34
Management serial clock
2.5 V
HSMA_SCL
AC3
J8 pin 35
JTAG clock signal
2.5 V
FPGA_JTAG_TCK
P5
J8 pin 36
JTAG mode select signal
2.5 V
FPGA_JTAG_TMS
P8
J8 pin 39
Dedicated CMOS clock out
2.5 V
HSMA_CLK_OUT0
Y7
J8 pin 40
Dedicated CMOS clock in
1.8 V
HSMA_CLK_IN0
AG14
J8 pin 41
Dedicated CMOS I/O bit 0
2.5 V
HSMA_D0
AB6
J8 pin 42
Dedicated CMOS I/O bit 1
2.5 V
HSMA_D1
AF2
J8 pin 43
Dedicated CMOS I/O bit 2
2.5 V
HSMA_D2
AE3
J8 pin 44
Dedicated CMOS I/O bit 3
2.5 V
HSMA_D3
AC5
J8 pin 47
LVDS TX or CMOS I/O bit 0
LVDS or 2.5 V
HSMA_TX_D_P0
R7
J8 pin 48
LVDS RX or CMOS I/O bit 0
LVDS or 2.5 V
HSMA_RX_D_P0
AB2
J8 pin 49
LVDS TX or CMOS I/O bit 0
LVDS or 2.5 V
HSMA_TX_D_N0
R6
J8 pin 50
LVDS RX or CMOS I/O bit 0
LVDS or 2.5 V
HSMA_RX_D_N0
AB1
J8 pin 53
LVDS TX bit 1p or CMOS I/O data 8
LVDS or 2.5 V
HSMA_TX_D_P1
V4
J8 pin 54
LVDS RX bit 1p or CMOS I/O data 9
LVDS or 2.5 V
HSMA_RX_D_P1
Y4
J8 pin 55
LVDS TX bit 1n or CMOS I/O data bit 10
LVDS or 2.5 V
HSMA_TX_D_N1
V3
J8 pin 56
LVDS RX bit 1n or CMOS I/O data bit 11
LVDS or 2.5 V
HSMA_RX_D_N1
Y3
J8 pin 59
LVDS TX bit 2p or CMOS I/O data bit 12
LVDS or 2.5 V
HSMA_TX_D_P2
T4
J8 pin 60
LVDS RX bit 2p or CMOS I/O data bit 13
LVDS or 2.5 V
HSMA_RX_D_P2
U3
J8 pin 61
LVDS TX bit 2n or CMOS I/O data bit 14
LVDS or 2.5 V
HSMA_TX_D_N2
T3
J8 pin 62
LVDS RX bit 2n or CMOS I/O data bit 15
LVDS or 2.5 V
HSMA_RX_D_N2
U4
J8 pin 65
LVDS TX bit 3p or CMOS I/O data bit 16
LVDS or 2.5 V
HSMA_TX_D_P3
R3
J8 pin 66
LVDS RX bit 3p or CMOS I/O data bit 17
LVDS or 2.5 V
HSMA_RX_D_P3
W2
J8 pin 67
LVDS TX bit 3n or CMOS I/O data bit 18
LVDS or 2.5 V
HSMA_TX_D_N3
R4
J8 pin 68
LVDS RX bit 3n or CMOS I/O data bit 19
LVDS or 2.5 V
HSMA_RX_D_N3
W1
J8 pin 71
LVDS TX bit 4p or CMOS I/O data bit 20
LVDS or 2.5 V
HSMA_TX_D_P4
M8
J8 pin 72
LVDS RX bit 4p or CMOS I/O data bit 21
LVDS or 2.5 V
HSMA_RX_D_P4
V2
J8 pin 73
LVDS TX or 4n CMOS I/O data bit 22
LVDS or 2.5 V
HSMA_TX_D_N4
M7
J8 pin 74
LVDS RX 4n or CMOS I/O data bit 23
LVDS or 2.5 V
HSMA_RX_D_N4
V1
J8 pin 77
LVDS TX 5p or CMOS I/O data bit 24
LVDS or 2.5 V
HSMA_TX_D_P5
P2
J8 pin 78
LVDS RX 5p or CMOS I/O data bit 25
LVDS or 2.5 V
HSMA_RX_D_P5
U2