Altera Cyclone III Development Board - Manual (Page 54)

2–44 Chapter 2: Board Components
Communication Ports and Interfaces
Cyclone III 3C120 Development Board Reference Manual © March 2009 Altera Corporation
J8 pin 79 LVDS TX 5n or CMOS I/O data bit 26 LVDS or 2.5 V HSMA_TX_D_N5 P1
J8 pin 80 LVDS RX 5n or CMOS I/O data bit 27 LVDS or 2.5 V HSMA_RX_D_N5 U1
J8 pin 83 LVDS TX 6p or CMOS I/O data bit 28 LVDS or 2.5 V HSMA_TX_D_P6 M4
J8 pin 84 LVDS RX 6p or CMOS I/O data bit 29 LVDS or 2.5 V HSMA_RX_D_P6 U6
J8 pin 85 LVDS TX 6n or CMOS I/O data bit 30 LVDS or 2.5 V HSMA_TX_D_N6 M3
J8 pin 86 LVDS RX 6n or CMOS I/O data bit 31 LVDS or 2.5 V HSMA_RX_D_N6 U5
J8 pin 89 LVDS TX 7p or CMOS I/O data bit 32 LVDS or 2.5 V HSMA_TX_D_P7 M2
J8 pin 90 LVDS RX 7p or CMOS I/O data bit 33 LVDS or 2.5 V HSMA_RX_D_P7 R2
J8 pin 91 LVDS TX 7n or CMOS I/O data bit 34 LVDS or 2.5 V HSMA_TX_D_N7 M1
J8 pin 92 LVDS RX 7n or CMOS I/O data bit 35 LVDS or 2.5 V HSMA_RX_D_N7 R1
J8 pin 95 LVDS or CMOS clock out LVDS or 2.5 V HSMA_CLK_OUT_P1 G6
J8 pin 96 LVDS or CMOS clock in LVDS or 2.5 V HSMA_CLK_IN_P1 Y2
J8 pin 97 LVDS or CMOS clock out LVDS or 2.5 V HSMA_CLK_OUT_N1 G5
J8 pin 98 LVDS or CMOS clock in LVDS or 2.5 V HSMA_CLK_IN_N1 Y1
J8 pin 101 LVDS TX 8p or CMOS I/O data bit 40 LVDS or 2.5 V HSMA_TX_D_P8 L7
J8 pin 102 LVDS RX 8p or CMOS I/O data bit 41 LVDS or 2.5 V HSMA_RX_D_P8 N4
J8 pin 103 LVDS TX 8n or CMOS I/O data bit 42 LVDS or 2.5 V HSMA_TX_D_N8 L6
J8 pin 104 LVDS RX 8n or CMOS I/O data bit 43 LVDS or 2.5 V HSMA_RX_D_N8 N3
J8 pin 107 LVDS TX 9p or CMOS I/O data bit 44 LVDS or 2.5 V HSMA_TX_D_P9 K8
J8 pin 108 LVDS RX 9p or CMOS I/O data bit 45 LVDS or 2.5 V HSMA_RX_D_P9 L4
J8 pin 109 LVDS TX 9n or CMOS I/O data bit 46 LVDS or 2.5 V HSMA_TX_D_N9 L8
J8 pin 110 LVDS RX 9n or CMOS I/O data bit 47 LVDS or 2.5 V HSMA_RX_D_N9 L3
J8 pin 113 LVDS TX 10p or CMOS I/O data bit 48 LVDS or 2.5 V HSMA_TX_D_P10 K4
J8 pin 114 LVDS RX 10p or CMOS I/O data bit 49 LVDS or 2.5 V HSMA_RX_D_P10 L2
J8 pin 115 LVDS TX 10n or CMOS I/O data bit 50 LVDS or 2.5 V HSMA_TX_D_N10 K3
J8 pin 116 LVDS RX 10n or CMOS I/O data bit 51 LVDS or 2.5 V HSMA_RX_D_N10 L1
J8 pin 119 LVDS TX 11p or CMOS I/O data bit 52 LVDS or 2.5 V HSMA_TX_D_P11 J4
J8 pin 120 LVDS RX 11p or CMOS I/O data bit 53 LVDS or 2.5 V HSMA_RX_D_P11 K2
J8 pin 121 LVDS TX 11n or CMOS I/O data bit 54 LVDS or 2.5 V HSMA_TX_D_N11 J3
J8 pin 122 LVDS RX 11n or CMOS I/O data bit 55 LVDS or 2.5 V HSMA_RX_D_N11 K1
J8 pin 125 LVDS TX 12p or CMOS I/O data bit 56 LVDS or 2.5 V HSMA_TX_D_P12 J7
J8 pin 126 LVDS RX 12p or CMOS I/O data bit 57 LVDS or 2.5 V HSMA_RX_D_P12 J6
J8 pin 127 LVDS TX 12n or CMOS I/O data bit 58 LVDS or 2.5 V HSMA_TX_D_N12 K7
J8 pin 128 LVDS RX 12n or CMOS I/O data bit 59 LVDS or 2.5 V HSMA_RX_D_N12 J5
J8 pin 131 LVDS TX 13p or CMOS I/O data bit 60 LVDS or 2.5 V HSMA_TX_D_P13 G2
J8 pin 132 LVDS RX 13p or CMOS I/O data bit 61 LVDS or 2.5 V HSMA_RX_D_P13 H4
J8 pin 133 LVDS TX 13n or CMOS I/O data bit 62 LVDS or 2.5 V HSMA_TX_D_N13 G1
J8 pin 134 LVDS RX 13n or CMOS I/O data bit 63 LVDS or 2.5 V HSMA_RX_D_N13 H3
Table 2–47. HSMC Port A Interface Signal Name, Description, and Type (Part 2 of 3)
Board
Reference Description I/O Standard
Schematic
Signal Name
Cyclone III
Device Pin
Number