Altera Cyclone III Development Board User Manual
Page 23

Chapter 2: Board Components
2–13
MAX II CPLD
© March 2009 Altera Corporation
Cyclone III 3C120 Development Board Reference Manual
A15
2.5 V
Bidirectional
USB_PHY_FD[3]
D12
2.5 V
Bidirectional
USB_PHY_FD[4]
B14
2.5 V
Bidirectional
USB_PHY_FD[5]
C11
2.5 V
Bidirectional
USB_PHY_FD[6]
B13
2.5 V
Bidirectional
USB_PHY_FD[7]
D11
2.5 V
Bidirectional
USB_PHY_FD[8]
A13
2.5 V
Bidirectional
USB_PHY_FD[9]
C4
2.5 V
Output
USB_PHY_FULL
C7
2.5 V
Input
USB_PHY_IFCLK
E6
2.5 V
Input
USB_PHY_REn
B4
2.5 V
Input
USB_PHY_WEn
E7
2.5 V
Input
USB_PWR_ENn
C8
2.5 V
Output
USB_RDn
A11
2.5 V
Input
USB_REn
C6
2.5 V
Output
USB_RESETn
A5
2.5 V
Output
USB_RSTn
D7
2.5 V
Input
USB_RSTOUTn
B6
2.5 V
Input
USB_RXFn
B5
2.5 V
Output
USB_SI_WU
K3
2.5 V
Input
USB_TXEn
C5
2.5 V
Output
USB_WAKEUP
M3
2.5 V
Input
USB_WEn
A6
2.5 V
Output
USB_WR
F10
—
Power
VCCINT
G11
—
Power
VCCINT
H8
—
Power
VCCINT
H10
—
Power
VCCINT
J7
—
Power
VCCINT
J9
—
Power
VCCINT
K6
—
Power
VCCINT
L7
—
Power
VCCINT
C1
—
Power
VCCIO1
H6
—
Power
VCCIO1
J6
—
Power
VCCIO1
P1
—
Power
VCCIO1
A3
—
Power
VCCIO2
A14
—
Power
VCCIO2
F8
—
Power
VCCIO2
F9
—
Power
VCCIO2
Table 2–5. MAX II Device Pin-Out
(Note 1)
(Part 7 of 8)
MAX II Pin Number
I/O Standard
Signal Direction
Schematic
Signal Name
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)