Altera Cyclone III Development Board - Manual (Page 57)

Chapter 2: Board Components 2–47
Communication Ports and Interfaces
© March 2009 Altera Corporation Cyclone III 3C120 Development Board Reference Manual
J9 pin 107 LVDS TX 9p or CMOS I/O data bit 44 LVDS or 2.5 V HSMB_TX_D_P9 W25
J9 pin 108 LVDS RX 9p or CMOS I/O data bit 45 LVDS or 2.5 V HSMB_RX_D_P9 R22
J9 pin 109 LVDS TX 9n or CMOS I/O data bit 46 LVDS or 2.5 V HSMB_TX_D_N9 W26
J9 pin 110 LVDS RX 9n or CMOS I/O data bit 47 LVDS or 2.5 V HSMB_RX_D_N9 R23
J9 pin 113 LVDS TX 10p or CMOS I/O data bit 48 LVDS or 2.5 V HSMB_TX_D_P10 Y25
J9 pin 114 LVDS RX 10p or CMOS I/O data bit 49 LVDS or 2.5 V HSMB_RX_D_P10 T25
J9 pin 115 LVDS TX 10n or CMOS I/O data bit 50 LVDS or 2.5 V HSMB_TX_D_N10 Y26
J9 pin 116 LVDS RX 10n or CMOS I/O data bit 51 LVDS or 2.5 V HSMB_RX_D_N10 T26
J9 pin 119 LVDS TX 11p or CMOS I/O data bit 52 LVDS or 2.5 V HSMB_TX_D_P11 AA25
J9 pin 120 LVDS RX 11p or CMOS I/O data bit 53 LVDS or 2.5 V HSMB_RX_D_P11 U27
J9 pin 121 LVDS TX 11n or CMOS I/O data bit 54 LVDS or 2.5 V HSMB_TX_D_N11 AA26
J9 pin 122 LVDS RX 11n or CMOS I/O data bit 55 LVDS or 2.5 V HSMB_RX_D_N11 U28
J9 pin 125 LVDS TX 12p or CMOS I/O data bit 56 LVDS or 2.5 V HSMB_TX_D_P12 AB25
J9 pin 126 LVDS RX 12p or CMOS I/O data bit 57 LVDS or 2.5 V HSMB_RX_D_P12 U22
J9 pin 127 LVDS TX 12n or CMOS I/O data bit 58 LVDS or 2.5 V HSMB_TX_D_N12 AB26
J9 pin 128 LVDS RX 12n or CMOS I/O data bit 59 LVDS or 2.5 V HSMB_RX_D_N12 V22
J9 pin 131 LVDS TX 13p or CMOS I/O data bit 60 LVDS or 2.5 V HSMB_TX_D_P13 Y23
J9 pin 132 LVDS RX 13p or CMOS I/O data bit 61 LVDS or 2.5 V HSMB_RX_D_P13 W28
J9 pin 133 LVDS TX 13n or CMOS I/O data bit 62 LVDS or 2.5 V HSMB_TX_D_N13 Y24
J9 pin 134 LVDS RX 13n or CMOS I/O data bit 63 LVDS or 2.5 V HSMB_RX_D_N13 W27
J9 pin 137 LVDS TX 14p or CMOS I/O data bit 64 LVDS or 2.5 V HSMB_TX_D_P14 AE27
J9 pin 138 LVDS TX 14p or CMOS I/O data bit 65 LVDS or 2.5 V HSMB_RX_D_P14 V23
J9 pin 139 LVDS RX 14n or CMOS I/O data bit 66 LVDS or 2.5 V HSMB_TX_D_N14 AE28
J9 pin 140 LVDS RX 14n or CMOS I/O data bit 67 LVDS or 2.5 V HSMB_RX_D_N14 V24
J9 pin 143 LVDS RX 15p or CMOS I/O data bit 68 LVDS or 2.5 V HSMB_TX_D_P15 W22
J9 pin 144 LVDS TX 15p or CMOS I/O data bit 69 LVDS or 2.5 V HSMB_RX_D_P15 AB27
J9 pin 145 LVDS RX 15n or CMOS I/O data bit 70 LVDS or 2.5 V HSMB_TX_D_N15 Y22
J9 pin 146 LVDS TX 15n or CMOS I/O data bit 71 LVDS or 2.5 V HSMB_RX_D_N15 AB28
J9 pin 149 LVDS RX 16p or CMOS I/O data bit 72 LVDS or 2.5 V HSMB_TX_D_P16 V21
J9 pin 150 LVDS TX 16p or CMOS I/O data bit 73 LVDS or 2.5 V HSMB_RX_D_P16 AC27
J9 pin 151 LVDS TX 16n or CMOS I/O data bit 74 LVDS or 2.5 V HSMB_TX_D_N16 W21
J9 pin 152 LVDS RX 16n or CMOS I/O data bit 75 LVDS or 2.5 V HSMB_RX_D_N16 AC28
J9 pin 155 LVDS or CMOS clock out LVDS HSMB_CLK_OUT_P2 AD27
J9 pin 156 LVDS or CMOS clock in LVDS HSMB_CLK_IN_P2 Y27
J9 pin 157 LVDS or CMOS clock out 2.5 V HSMB_CLK_OUT_N2 AD28
J9 pin 158 LVDS or CMOS clock in 2.5 V HSMB_CLK_IN_N2 Y28
Table 2–48. HSMC Port B Interface Signal Name, Description, and Type (Part 3 of 4)
Board
Reference Description I/O Standard
Schematic
Signal Name
Cyclone III
Device Pin
Number