Altera Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 25)

Chapter 6: Board Test System 6–5
Using the Board Test System
July 2012 Altera Corporation Transceiver Signal Integrity Development Kit
Stratix V GX Edition User Guide
MAX II Registers
The MAX II registers control allows you to view and change the current MAX II
register values as described in
Table 6–1 . Changes to the register values with the GUI
take effect immediately.
■ SRST —Resets the system and reloads the FPGA with a design from flash memory
based on the other MAX II register values. Refer to Table 6–1 for more information.
■ PSO —Sets the MAX II PSO register. The following options are available:
■ Use PSR —Allows the PSR to determine the page of flash memory to use for
FPGA reconfiguration.
■ Use PSS —Allows the PSS to determine the page of flash memory to use for
FPGA reconfiguration.
■ PSR —Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to Table 6–1
for more information.
■ PSS —Displays the MAX II PSS register value. Refer to Table 6–1 for the list of
available options.
1
Because the System Info tab requires that a specific design is running in the FPGA at
a specific clock speed, writing a 0 to SRST or changing the PSO value can cause the
Board Test System to stop running.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Stratix V GX device is always the first device in the chain.
1 When set to 0, switch S7.6 (MAX BYPASS) includes the MAX II device in the JTAG
chain; when set to 1, the MAX II device is removed from the JTAG chain.
Table 6–1. MAX II Registers
Register Name
Read/Write
Capability
Description
System Reset
(SRST)
Write only Set to 0 to initiate an FPGA reconfiguration.
Page Select Override
(PSO)
Read / Write
When set to 0, the value in PSR determines the page of
flash memory to use for FPGA reconfiguration. When set to
1, the value in PSS determines the page of flash memory to
use for FPGA reconfiguration.
Page Select Switch
(PSS)
Read only
Holds the current value of jumper J28 PGMSEL:
1 = user image
2 = factory image.
Page Select Register
(PSR)
Read / Write
Determines which of the up to eight (0-7) pages of flash
memory to use for FPGA reconfiguration. The flash memory
ships with pages 0 and 1 preconfigured.