Altera Signal Integrity Development Kit, Stratix V GX Edition - Manual (Page 22)

6–2 Chapter 6: Board Test System
Preparing the Board
Transceiver Signal Integrity Development Kit July 2012 Altera Corporation
Stratix V GX Edition User Guide
Several designs are provided to test the major board features. Each design provides
data for one or more tabs in the application. The Configure menu identifies the
appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears and allows you to
exercise the related board features. Highlights appear in the board picture around the
corresponding components.
1
The Board Test System and Power Monitor share the JTAG bus with other
applications like the Nios II debugger and the SignalTap
® II Embedded Logic
Analyzer. Because the Quartus II programmer uses most of the bandwidth of the
JTAG bus, other applications using the JTAG bus might time out. Be sure to close the
other applications before attempting to reconfigure the FPGA using the Quartus II
Programmer.
Preparing the Board
With the power to the board off, following these steps:
1. Connect the USB cable to the board.
1
If you connect an external USB-Blaster download cable and power cycle the
board, the on-board Blaster is disconnected and the S5_UNLOCK function
(
Table 4–3 on page 4–4 ) does not allow JTAG access to the FPGA. To
successfully use the USB-Blaster cable, disconnect it before power cycling
the board. After you power cycled the board, then reconnect the
USB-Blaster cable.
2. Ensure that the development board DIP switches are set to the default positions as
shown in the “Factory Default Switch Settings” section starting on page 4–2 .
3. Install a jumper at the user position (jump pins 1-2) of the Load Selector (J28)
jumper block.
f For more information about the board’s DIP switch and jumper settings,
refer to the
Transceiver Signal Integrity Development Kit Stratix V GX Reference
Manual .
4. Turn on the power to the board. The board loads the design stored in the user
portion of flash memory into the FPGA. If your board is still in the factory
configuration, or if you have downloaded a newer version of the Board Test
System to flash memory through the Board Update Portal, the design loads the
GPIO,SRAM, and flash memory tests.
c
To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The application
cannot run correctly unless the USB cable is attached and the board is on.