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Altera PowerPlay Early Power Estimator User Manual

Page 25

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Altera Corporation

3–7

January 2007

PowerPlay Early Power Estimator For Stratix II, Stratix II GX & HardCopy II

Using the PowerPlay Early Power Estimator

Toggle %

Enter the average percentage of logic toggling on each clock cycle. The toggle
percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%, which
is the toggle percentage of a 16-bit counter. To ensure you do not underestimate the
toggle percentage, you can use a higher toggle percentage. Most logic only toggles
infrequently, and hence toggle rates of less than 50% are more realistic.

For example, a TFF with its input tied to V

CC

has a toggle rate of 100% because its

output is changing logic states on every clock cycle (

Figure 3–2

).

Figure 3–3

shows

an example of a 4-bit counter. The first TFF with least significant bit (LSB) output

cout0

has a toggle rate of 100% because the signal toggles on every clock cycle.

The toggle rate for the second TFF with output

cout1

is 50% since the signal only

toggles on every two clock cycles. Consequently, the toggle rate for the third TFF with
output

cout2

and fourth TFF with output

cout3

are 25% and 12.5%, respectively.

Therefore, the average toggle percentage for this 4-bit counter is (100 + 50 + 25 +
12.5)/4 = 46.875%.

Routing

This shows the power dissipation due to estimated routing (in W).

Routing power is highly dependent on placement and routing, which is itself a function
of design complexity. The values shown are representative of routing power based on
experimentation on over 100 designs.

Use the Quartus II PowerPlay Power Analyzer for detailed analysis based on the
routing used in your design.

Block

This shows the power dissipation due to internal toggling of the ALMs (in W).

Logic block power is a function of the function implemented and relative toggle rates
of the various inputs. The PowerPlay Early Power Estimator spreadsheet uses an
estimate based on observed behavior across over 100 real-world designs.

Use the Quartus II PowerPlay Power Analyzer for accurate analysis based on the
exact synthesis of your design.

Total

This shows the total power dissipation (in W). The total power dissipation is the sum
of the routing and block power.

User Comments

Enter any comments. This is an optional entry.

Table 3–2. Logic Section Information (Part 2 of 2)

Column Heading

Description