MUTEC iClock - Manual (Page 33)

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Manual SDs-01 D 3.2.2003 17:45 Uhr Seite 3
Example
iCLOCK is synchronized by an external Word
Clock reference with 44.1kHz. The outputs
are adjusted to different clock rates (see
adjacent diagramm). If the external reference
changes to 48.0kHz, the predefined outgoing
clock rates will remain unchanged!
The reason is that iCLOCK‘s intelligent synthesis
process synchronizes every reference signal
phase-locked and converts it simultaneously
into the adjusted output clock rates. Thus the
typical signal distribution effect, »a change
of input clock rate changes all output clock
rates«, is prevented in general. The adjusted
output clock rates are permanently available,
not depending on the frequency or format of
the incoming reference!
iCLOCK TECHNOLOGY
Functional Principle
iCLOCK‘s principle operation is completely different to conventional
products. The customer, as a matter of priority, defines the clock rates and
formates which are constantly available at the outputs – not depending on
the incoming reference signals! Limitations regarding defined combinations
of input and output clock signals do not exist for iCLOCK. All inputs and
outputs can be routed and combined freely.
33
Furthermore, unlike standard clock generators, iCLOCK‘s unique concept
enables to set all system functions during any operation mode. This is
regardless of whether the synthesizer is synchronized internally or by an
external source. Doing this, the powerful synthesis process enables additio-
nally, as an outstanding feature, the use of the pull up/down and varispeed
functions simultaneously! Thus any conceivable adaption of the outgoing
basic clock rates is possible with iCLOCK.
During this process the system detects automatically useful phase relation-
ships between the reference input and generated output signals. Adjust-
ments aligned to AES11-1997/2003 and EBU R83-1996 will be executed in
realtime independently.
SoftReLock
SoftReLock is a special system routine executed by the synthesizer in every
operation mode of reference change or reference resynchronization.
Especially in cases of the later described SEQSYNC or CYCLESYNC functions,
SoftReLock guarantees a gradual and seamless synchronization update of
the internal signal generators, or all iCLOCK output signals respectively,
to the basic clock rate of a new or reestablished reference source. Also if
complete different reference types of unequal sources are synchronized
in succession, e.g. NTSC video after pulled down 48.0kHz AES11, the
SoftReLock routine ensures interruption-free and gently adjustment of
iCLOCK‘s output signals to the new reference.
SoftReLock represents one of the most important functions to support
the system‘s ability providing continous clock supply under all imaginable
operation modes.
Output WCLK
176.4kHz
Functional principle during input reference change
Output WCLK
32.0kHz
Output WCLK
192.0kHz
Output WCLK
44.1kHz
Output WCLK
48.0kHz
Input Reference Change
44.1kHz to 48.0kHz