MUTEC iClock User Manual

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Manual SDs-01 D 3.2.2003 17:45 Uhr Seite 16

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S/PDIF outputs, page 2

DIST does not provide redundancy for the
S/P-DIF outputs. If the external S/P-DIF or
AES3/-11 signal source fails, the S/P-DIF
output pair will fail, too!

Due to the internal signal phase corrections
the synthesizer can re-lock temporarily
when switching S/P-DIF clock frequencies.
This does not affect the output signals or
functionality of iCLOCK.

S/P-DIF clock rates are set independently
of externally applied clocks. Thus, iCLOCK
provides S/P-DIF clock conversion from all
supported input rates to all generatable
output rates!

S/PDIF OUT /1, -/2

(page name)

The page names refer to the respective S/P-DIF menu page (see above
figures).

Functions and settings on the first S/P-DIF output page:

FREQ

(function)

FREQUENCY Sets the clock rate of the S/P-DIF outputs. A so-called S/P-DIF
clear frame signal (in compliance with AES11) is generated. This signal
does not contain any audio information (data bits). The factory default is
44.1kHz.

16.0...192.0kHz

(setting)

Altogether twelve different clock rates between 16.0 kHz and 192.0 kHz
can be selected. Refer to the »Synchronizable and Generatable Clock Rates«
section in the appendix for a full list of all clock rates.

DIST

(setting)

DISTRIBUTION This setting allows for forwarding an input S/P-DIF or
AES3/-11 signal to the S/P-DIF output pair using a hardware bypass. As no
adjustments can be made in this mode, the other functions and parameters
will be hidden, and the second menu page of the S/P-DIF pair will not be
accessible; the parameters and functions can only be accessed after the
internal S/P-DIF generator has been enabled by selecting a different clock
rate.

In this mode, the synthesizer synchronizes to the input S/P-DIF or AES3/-11
signal; thus, the video and audio clock signals provided at the other outputs
are linked with phase lock to the input signal.

WORDL

(function)

WORD LENGTH This function allows for changing the word length stored in
the channel status bits of the S/P-DIF clear-frame signal.
The factory default is 24BITs.

16BITs, 18BITs, 20BITs, 24BITs

(setting)

One of four word lengths between 16 and 24Bits are available for selection.

S/PDIF outputs, page 1

LOCKSTAT

(function)

LOCK STATUS This function allows for changing the synchronization status
stored in the channel status bits (byte 0, bit 5) of the clear-frame signal of
the selected AES/EBU output pair. The factory default is LOCKED.

If the selected AES/EBU output pair is operated in consumer mode, this
parameter is not available due to the modified structure of the channel-
status bits!

LOCKED, UNLOCKED

(Parameter)

LOCKED, UNLOCKED These settings allow for toggling between the locked
and unlocked statuses.

Configuring the S/P-DIF Outputs

A clock rate can be set for both S/P-DIF outputs similarly. The channel-status
bits can be modified, too.

This manual is related to the following products:

iClock dp