MUTEC iClock User Manual

Page 24

\\\\\\\\\\\\\\\\\\

A N H A N G

> > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >

Manual SDs-01 D 3.2.2003 17:45 Uhr Seite 16

FORMAT

(function)

FORMAT This function allows for altering the S/P-DIF format stored in the
channel status bits (byte 0, bit 0) of the S/P-DIF blank frame signal. The
factory default is CONS.

PROF, CONS

(setting)

PROF, CONS This setting allows for toggling the S/P-DIF blank frame signal
between consumer (CONS) and professional (PROF) formats.

DCSET

(function)

DC-OFFSET This function allows for applying a DC-offset signal level of ap-
prox. 200 mV to the output S/P-DIF blank frame signal. The factory default
is OFF.

ON, OFF

(setting)

This will enable (ON) or disable (OFF) the DC-offset signal level in the S/P-
DIF blank frame signal.

Functions and settings on the second S/P-DIF output page:

AUDIOSTAT

(function)

AUDIOSTATUS This function allows for setting the audio status stored in
the channel status bits (byte 0, bit 1) of the S/P-DIF blank frame signal. The
factory default is NONAUDIO.

NORMAUDIO, NONAUDIO

(setting)

These settings allows for selecting the norm-audio or non-audio statuses.

REFSTAT

(function)

REFERENCE STATUS This function allows for changing the reference status
stored in the channel status bits (byte 3, bits 4, 5) of the clear-frame signal
of the selected S/P-DIF output pair. The factory default is LEVEL 3.

LEVEL 3

(setting)

With the LEVEL 3 (variable) setting, the S/P-DIF blank frame signal is output
with no information on clock accuracy.

LEVEL 2

(setting)

With the LEVEL 2 setting, the S/P-DIF blank frame signal is output with a
clock accuracy of ±1000 ppm.

LEVEL 1

(setting)

With the LEVEL 2 setting, the S/P-DIF blank frame signal is output with a
clock accuracy of ±50 ppm.

If the professional format is selected,
the physical parameters of the output
terminals (unbalanced operation, level, and
impedance) will remain unchanged!

The functions and settings displayed on
the S/P-DIF menu pages are automatically
adapted with regard to the channel-status
bits of the professional format.

Example

There are S/P-DIF receiver circuits causing
problems when synchronizing to S/P-DIF blank
frame signals. This usually results in increased
jitter and signal instabilities. Enabling a DC-
offset level in the S/P-DIF blank frame signal
will allow for synchronizing any S/P-DIF input
stage. This level can normally be processed wit-
hout problems by the concerning S/P-DIF input
stages, thus ensuring reliable synchronization.

This manual is related to the following products:

iClock dp