Digilent DDR-2 Opus Card - Manual (Page 5)

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 5 Copyright © 2009-2010 by CML
2. State Machine for Writing Data to Memory
This chapter covers the state machine that controls the writing of data sent via the PLB bus to the
DDR-2 Memory Controller. The write state machine supports both non-burst writes and burst
writes. Burst writes are limited to a multiple of four 32-bit words or a multiple of two 64-bit
words depending on the width of the PLB data bus and should be limited to a maximum length
of eight quad-words (128 bytes). Each burst is assumed to have consecutive addresses starting
with an address masked by 0xFFFFFFF0. Burst writes also assume that all bytes in the burst are
to be written (i.e. bus2IP_BE is all 1’s).
2.1 Signal Definitions
The table below provides details on the signals used for writing data to memory.
Name
I/O Description
Bus2IP_Clk I The clock for the PLB bus (currently 100 MHz)
DDR2_Clk I The clock for the DDR-2 memory (currently 200 MHz)
Bus2IP_Reset I Reset signal for the block
App_AF_AFull I Indicates the DDR-2 address buffer is full – not currently used
App_WDF_AFull I Indicates the DDR-2 data buffer is full – not currently used
Bus2IP_Addr I Address of memory to write to
Bus2IP_CS I Indicates the DDR-2 memory is being accessed
Bus2IP_Burst I Indicates a burst read or write is occurring
Bus2IP_RNW I Indicates a write access when low
Bus2IP_WrReq I Indicates a write request
Bus2IP_BE I Indicates bytes to write to (big endian format)
Bus2IP_Data I Data to be written to memory
Rd_Send_Ack I Indicates the read from the PLB slave should be acknowledged
on the next clock cycle.
Rd_Send_Cmd I Indicates the read command and address should be sent to the
DDR-2 memory controller on the next clock cycle.
App_AF_WREn O Causes a write to the DDR-2 address buffer on the rising edge
of DDR2_Clk
App_WDF_WREn O Causes a write to the DDR-2 data buffer on the rising edge of
DDR2_Clk – must write enough data for four consecutive
addresses
App_AF_Cmd O The command to be written to the DDR-2 controller (a Write
command)
App_AF_Addr O The first address that is written to in the DDR-2 memory
App_WDF_Data O The data to be written to the DDR-2 memory
App_WDF_Mask_Data O The mask for the data being writing to the DDR-2 controller
(big endian format)
IP2Bus_RdAck O Acknowledges that the read to memory has occurred
IP2Bus_WrAck O Acknowledges that the write to memory has occurred
IP2Bus_AddrAck O Acknowledges that the address to write to has been latched