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Digilent DDR-2 Opus Card User Manual

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Opus Card – DDR-2 Interface

Reference Manual

Table of Contents

12/03/2010 07:35 AM

2

Copyright © 2009-2010 by CML

1. INTRODUCTION ..................................................................................................................................................3

1.1 D

EBUG

R

EGISTERS

A

CCESSIBLE BY THE

CPU .....................................................................................................3

1.2 C

ONFIGURATION

R

EGISTER

A

CCESSIBLE BY THE

CPU........................................................................................3

1.3 E

NDIANNESS

........................................................................................................................................................3

1.4 DDR-2 M

EMORY

A

CCESSIBLE BY THE

CPU .......................................................................................................4

2. STATE MACHINE FOR WRITING DATA TO MEMORY.............................................................................5

2.1 S

IGNAL

D

EFINITIONS

...........................................................................................................................................5

2.2 W

RITE

S

TATE

M

ACHINE

......................................................................................................................................6

2.3 W

AVEFORMS

.......................................................................................................................................................7

2.3.1 Non-burst, 32-bit Memory Write .................................................................................................................7

2.3.2 Non-burst, 64-bit Memory Write .................................................................................................................8

2.3.3 Burst Memory Write - Four 32-bit Words ...................................................................................................9

2.3.4 Burst Memory Write - Eight 32-bit Words.................................................................................................10

2.3.5 Burst Memory Write – Two 64-bit Words..................................................................................................11

2.3.6 Burst Memory Write - Four 64-bit Words .................................................................................................12

3. STATE MACHINES FOR READING DATA FROM MEMORY..................................................................13

3.1 S

IGNAL

D

EFINITIONS

.........................................................................................................................................13

3.2 R

EAD

S

TATE

M

ACHINE

.....................................................................................................................................14

3.2 R

EAD

FIFO S

TATE

M

ACHINE

............................................................................................................................15

3.3 W

AVEFORMS

.....................................................................................................................................................16

3.3.1 Non-burst, 32-bit Memory Read Clock-Aligned ........................................................................................16

3.3.2 Non-burst, 32-bit Memory Read not Clock-Aligned ..................................................................................17

3.3.3 Non-burst, 64-bit Memory Read ................................................................................................................18

3.3.4 Burst Memory Read - Four 32-bit Words ..................................................................................................19

3.3.5 Burst Memory Read - Eight 32-bit Words .................................................................................................20

3.3.6 Burst Memory Read - Two 64-bit Words ...................................................................................................21

3.3.7 Burst Memory Read - Four 64-bit Words ..................................................................................................22