Digilent DDR-2 Opus Card - Manual (Page 3)

Opus Card – DDR-2 Interface
Reference Manual
12/03/2010 07:35 AM 3 Copyright © 2009-2010 by CML
1. Introduction
This document provides the details on how DDR-2 memory on the Opus card is connected into
the PLB bus contained in the Xilinx Virtex-5 FPGA using the Embedded Design Kit (EDK).
The CML team discovered that the default Multi-Port Memory Controller (MPMC) provided
with the EDK had problems which reduced the reliability of accessing the DDR-2 memory
contained on the Opus card.
For additional details on many of the registers described here, see document DS562 from Xilinx.
This Xilinx document is titled “PLBV46 Slave Burst”. In addition, there are further details on
the DDR-2 memory controller generated using Xilinx MIG in document UG086 that is titled
“Memory Interface Solutions User Guide”.
1.1 Debug Registers Accessible by the CPU
There are several debug registers that can be read via the CPU to determine the calibrated state
of the DDR-2 PHY. These registers are detailed below:
• 0x84800000 – DQ IODELAY settings for bits 3 downto 0
• 0x84800004 – DQ IODELAY settings for bits 7 downto 4
• 0x84800008 – DQ IODELAY settings for bits 11 downto 8
• 0x8480000C – DQ IODELAY settings for bits 15 downto 12
• 0x84800010 – DQ IODELAY settings for bits 19 downto 16
• 0x84800014 – DQ IODELAY settings for bits 23 downto 20
• 0x84800018 – DQ IODELAY settings for bits 27 downto 24
• 0x8480001C – DQ IODELAY settings for bits 31 downto 28
• 0x84800020 – DQS IODELAY settings
• 0x84800024 – Gate Tap IODELAY settings
• 0x84800028 – Read Data Enable (RDEn) delay and Data Select IODELAY settings
• 0x8480002C – Gate delay settings
1.2 Configuration Register Accessible by the CPU
There is one configuration register that can be set via the CPU. This configuration register
controls the reset of the external Ethernet PHY and memory burst accesses. In big endian
format, bit 30 resets the Ethernet PHY when set to ‘1’ and bit 31 enables burst mode when set to
‘1’. Besides a hardware reset, the only way to clear these bits is by a write to the configuration
register. So, it is important to clear bit 30 by a write to the configuration register after the
required 100uS have elapsed to bring the Ethernet PHY out of reset mode.
1.3 Endianness
The PLB slave assumes a big endian interface to memory. Therefore, memory is organized in a
big endian fashion where byte 0 is in bits 0 to 7, byte 1 is in bits 8 to 15 and so forth where bit 0
is the most significant bit in a word.