Power sequencing, Advanced power management – Ampro Corporation LITTLE BOARD 5001451A User Manual
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Table 2-31. Flat Panel Video Connector (J15)
Pin #
Signal Name
Description
1
SHFCLK
Shift Clock. Pixel clock for flat panel data.
2
M DE
M signal for panel AC drive control. Sometimes called ACDCLK or AC
Drive. May also be configured to be -BLANK or as Display Enable (DE)
for TFT panels.
3
LP
Latch Pulse. Sometimes called Load Clock, Line Load, or Input Data
Latch. It’s the flat panel equivalent of HSYNC.
4
FLM
First Line Marker. Also called Frame Sync or Scan Start-up. Flat panel
equivalent to VSYNC.
5,6
GND
Ground
7-30
FP0-FP23
Flat panel video data 0 through 23 (in order).
31
ENAVDD
Enable Vdd. Power sequencing control for panel driver electronics Vdd.
Active high.
32
ENAVEE
Enable Vee, active high. Power sequencing control for panel bias
voltage. This signal is sent to the optional Vee supply board to control
Vee output.
33
+3.3V
Panel power
34
+12V
+12 Volt supply (from J10)
35,36
GND
Ground
37
ENABLK
Enable backlight. Power control for panel backlight. Active high.
38
+5.0V
From Little Board P6d module.
39-50
FP24-FP35
Flat panel video data 24 through 35 (in order).
Power Sequencing
Some LCD flat panel displays can be damaged if the voltage and data signals are applied at power
up. This can result in damage to the panel or reduction of its operational life. The LB P6d module
provides the control signals for switching the power supply lines to protect the flat panel. Power to
the panel must be enabled using the special enable signals provided on the flat panel connector,
ENAVEE, ENAVDD, and ENABKL.
Advanced Power Management
The same signals that support power sequencing are also used to provide the power management
feature. In “panel off mode” both the CRT and flat panel interfaces are turned off, but the VGA
subsystem (registers and display memory) remain powered. In “standby mode”, the CRT and flat
panel interfaces are turned off, and in addition, the VGA subsystem is turned off. The screen
DRAM is placed in a low-power mode in which only the DRAM is refreshed.