An372 – Cirrus Logic AN372 User Manual
Page 13
AN372
AN372REV1
13
Initially, T3 is assumed to be zero. After the circuit is built, the oscillation period can be measured, and the
circuit parameters can be tuned to assure full power at the nominal switching frequency. Setting T3 to zero
defines the total switching period TT as:
solving for the critical duty cycle
C
using Equation 7 and Equation 8 yields:
where
C
= Critical duty cycle
For a normal buck topology N = 0 and Equation 9 reduces to:
Typically 180V < V
BST
< 450V and V
OUT
< 30V. The effect N has on the numerator of
C
is greater than it is
on the denominator. Therefore, an estimate of
C
is roughly proportional to N. Increasing N increases period
T1 and decreases period T2, which decreases the peak current I
PK(FB)
in the FET but increases the peak
current in the second stage catch diode D3.
Step 6) Determine the Buck Nominal Timing T1 and T2
Equation 11 and Equation 12 express T1 and T2 from TT and
∆
C
, accounting for the effect of non-zero T3.
Solve for T1 and T2 using Equation 11 and Equation 12, respectively:
Step 7) Calculate Peak Current on the Buck Primary-side
Calculate I
PK(FB)
using Equation 13:
where
TT
fb
= Switching period at full brightness (full load condition)
T1
fb
= Period T1 at full brightness (full load condition)
Use values that yield the highest I
PK(FB).
Step 8) Calculate R
Sense
(R21)
Calculate sense resistor R
Sense
(R21) for buck using Equation 14:
where
R21 = R
Sense
in
TT
T1 T2
+
=
[Eq. 8]
C
T1
TT
-------
=
V
OUT
N 1
+
N V
OUT
V
BST
+
--------------------------------------------------
=
[Eq. 9]
C
V
OUT
V
BST
--------------
=
[Eq. 10]
T1
1
F
SW
----------- T3
–
V
Reflected
V
Reflected
V
BST
+
----------------------------------------------------
=
[Eq. 11]
T2
1
F
SW
----------- T3
–
V
BST
V
Reflected
V
BST
+
----------------------------------------------------
=
[Eq. 12]
I
PK FB
2 P
OUT max
TT
fb
V
BST
T1
fb
----------------------------------------------
=
[Eq. 13]
R
Sense
1.4
I
PK FB
------------------
=
[Eq. 14]