Cirrus Logic AN372 - Manual (Page 11)

AN372
AN372REV1 11
For optimum efficiency, the increase in conduction losses (created by an uneven duty cycle) must balance the
reduction of the losses caused by discharging the leakage inductance (obtained by increasing the overshoot
voltage). Equation 3 is used to balance all voltages contributing to the FET voltage drain and source.
where
V
Overshoot
= V
CLAMP
- V
Reflected
Step 4) Determine the Buck Inductor Turns Ratio
Select a turns ratio based on the output voltage, V
OUT
, and V
Reflected
using Equation 4.
where
V
OUT(max)
= The maximum LED string forward voltage V
OUT
at full current plus the rectifying diode voltage V
F
Step 5) Select the Full Brightness Switching Frequency
The CS1612/13 maximum switching frequency is 200kHz. Test results indicate that optimal performance is
obtained in the range of 75kHz to 120kHz. Higher frequencies allow the use of smaller magnetics, but
switching losses increase. Selecting too low a full brightness switching frequency risks impairing dimmer
compatibility while also allowing the minimum frequency to drop into the audible range.
From the full brightness frequency, determine the value of (T1+T2) using Equation 5.
where
T3 is 1/2 the resonant period
The boost inductance resonates with the total parasitic capacitance of the drain node. For initial calculations,
T3 is estimated as 1
s and must be measured for final accuracy.
During full brightness circuit operation, the circuit is delivering full nominal power to the LED string. When Q4
turns ‘ON’, current flows through the LED string, the entire inductor L winding (N+1), FET Q4, and resistor
R
Sense
(R21).
The current rises linearly from zero to a preset maximum value I
PK(FB)
defined by R
Sense
and the internal IC
threshold. The gate is driven high for as long as is required to reach I
PK(FB)
. The controller has a maximum T1
(‘ON’ time) limit set to 8.8 s, after which the gate is turned ‘OFF’.
Just before the gate turns ‘OFF’ the inductor has a field strength of ((N+1) I
PK(FB)
). When the gate turns
‘OFF’, the field cannot change abruptly, despite the fact that current no longer flows though N turns. Therefore,
a current equal to ((N+1)
I
PK(FB)
) must flow in the single turn left in the circuit. A tapped inductor enables
current multiplication in the load path in exchange for a longer rise time T1 and higher reflected voltage across
the FET (see Figure 6).
During time T2, the inductor current decays linearly, transferring to the load the energy stored in the inductor.
At the end of time T2, the current in the inductor is zero. However, some energy is stored in parasitic
capacitance C
P
charged to ((N+1) V
OUT
). Capacitance C
P
and inductance L oscillate until the losses exhaust
the energy stored in C
P
. By turning ‘ON’ the FET Q4 at the end of the first half of the oscillation, most of the
energy is still stored in the capacitor and with the right voltage polarity to facilitate the charge to (V
BST
-V
OUT
)
required by a new cycle start.
This mode of operation with minimal time between the end of time T2 and the new cycle start is called quasi-
resonant and is maintained only at full power or near full power. At lower power levels, one or more extra
oscillations are allowed before turning ‘ON’ the FET Q4 at the next valley. Extending the idle time T3, when no
V
Breakdown
V
BST
V
Reflected
V  +
CLAMP
V
Reflected
 – V
M in arg
+ + = [Eq. 3]
N
V
Reflected
V
OUT max  
---------------------------- = [Eq. 4]
T1 T2 +
1
F
SW
-----------
 
  T3
– = [Eq. 5]