Cirrus Logic CS8952 - Manual (Page 8)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 8
DS206F1
100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES
Parameter Symbol Min Typ Max Unit
RX_CLK Period t
P
- 40 - ns
RX_CLK Pulse Width t
WL,
t
WH
- 20 - ns
RXD[3:0],RX_ER/RXD4,RX_DV setup to rising
edge of RX_CLK t
SU
10 - - ns
RXD[3:0],RX_ER/RXD4,RX_DV hold from rising
edge of RX_CLK t
HD
10 - - ns
CRS to RXD latency 4B Aligned
5B Aligned t
DLAT
2
2 3 - 6
3 - 6 8
8 BT
“Start of Stream” to CRS asserted t
CRS1
- 10 11 BT
“End of Stream” to CRS de-asserted t
CRS2
- - 21 BT
“Start of Stream” to COL asserted t
COL1
- - 11 BT
“End of Stream” to COL de-asserted t
COL2
- - 21 BT
RX_EN asserted to RX_DV, RXD[3:0] valid t
EN
- TBD - ns
RX_EN de-asserted to RX_DV, RXD[3:0].
RX_ER/RXD4 in high impedance state t
DIS
- TBD - ns
RX_CLK
RXD[3:0],
CRS
t
CRS1
t
COL2
t
RLAT
Start of
Stream
End of
Stream
RX_EN
RX+/-
RX_DV
IN
OUT
IN
OUT
OUT
OUT
OUT COL
t
COL1
t
CRS2
t
HD
t
EN
t
DIS
RX_ER/RXD4
t
WL
t
WH
t
P
t
SU