Cirrus Logic CS8952 User Manual
Features, Description, Extremely low transmit jitter (<400 ps)
Copyright
© Cirrus Logic, Inc. 2007
(All Rights Reserved)
http://www.cirrus.com
Features
z
Single-Chip IEEE 802.3 Physical Interface IC for
100BASE-TX, 100BASE-FX and 10BASE-T
z
Adaptive Equalizer provides Extended Length
Operation (>160 m) with Superior Noise
Immunity and NEXT Margin
z
Extremely Low Transmit Jitter (<400 ps)
z
Low Common Mode Noise on TX Driver for
Reduced EMI Problems
z
Integrated RX and TX Filters for 10BASE-T
z
Compensation for Back-to-Back “Killer Packets”
z
Digital Interfaces Supported
– Media Independent Interface (MII) for 100BASE-X
and 10BASE-T
– Repeater 5-bit code-group interface (100BASE-X)
– 10BASE-T Serial Interface
z
Register Set Compatible with DP83840A
z
IEEE 802.3 Auto-Negotiation with Next Page
Support
z
Six LED drivers (LNK, COL, FDX, TX, RX, and
SPD)
z
Low power (135 mA Typ) CMOS design operates
on a single 5 V supply
Description
The CS8952 uses CMOS technology to deliver a high-
performance, low-cost 100BASE-X/10BASE-T Physical
Layer (PHY) line interface. It makes use of an adaptive
equalizer optimized for noise and near end crosstalk
(NEXT) immunity to extend receiver operation to cable
lengths exceeding 160 m. In addition, the transmit cir-
cuitry has been designed to provide extremely low
transmit jitter (<400 ps) for improved link partner perfor-
mance. Transmit driver common mode noise has been
minimized to reduce EMI for simplified FCC certification.
The CS8952 incorporates a standard Media Indepen-
dent Interface (MII) for easy connection to a variety of 10
and 100 Mb/s Media Access Controllers (MACs). The
CS8952 also includes a pseudo-ECL interface for use
with 100Base-FX fiber interconnect modules.
ORDERING INFORMATION
TX_EN
TX_ER/TXD4
TXD[3:0]
TX_CLK
MDC
MII_IRQ
MDIO
CRS
COL
RX_ER/RXD4
RX_DV
RXD[3:0]
RX_CLK
RX_EN
TX+,
TX-
TX_NRZ+,
TX_NRZ-
RX_NRZ+,
RX_NRZ-
RX+,
RX-
LED1
LED2
LED3
LED4
LED5
10/100
M
U
X
4B/5B
Decoder
Descrambler
Manchester
Encoder
Scrambler
Fiber NRZI
Interface
MLT-3
Encoder
10BaseT
Filter
Slew Rate
Control
M
U
X
10/100
4B/5B
Encoder
ECL Driver
ECL Receiver
Adaptive Eq. &
Baseline Wander
Compensation
10BaseT
Filter
LED
Drivers
100BaseT
Slicer
10BaseT
Slicer
Fiber NRZI
Interface
MLT-3
Decoder
Manchester
Decoder
Auto
Negotiation
Timing
Recovery
MII
Control/Status
Registers
Link
Management
CS8952 10BaseT/100Base-X
Transceiver
Medi
a I
ndepen
dent
I
n
ter
fac
e
(M
II
)
JAN ‘07
DS206F1
CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
Document Outline
- Features & Description
- 1. Specifications and Characteristics
- Absolute Maximum Ratings
- Recommended Operating Conditions
- Quartz Crystal Requirements
- DC Characteristics
- 10Base-T characteristics
- 100Base-X Characteristics
- 100Base-TX MII receive timing - 4b/5B Aligned modes
- 100Base-TX MII receive timing - 5b Bypass Align mode
- 100Base-TX MII Transmit timing - 4b/5B Align modes
- 100Base-TX MII Transmit timing - 5B BYpass Align mode
- 10Base-t MII receive timing
- 10Base-t MII Transmit timing
- 10Base-t SERIAL receive timing
- 10Base-t SERIAL Transmit timing
- Auto Negotiation / Fast Link Pulse Timing
- Serial Management Interface timing
- 2. Introduction
- 3. Functional Description
- 4. Media Independent Interface (MII)
- 5. Configuration
- 6. CS8952 Registers
- 7. Design Considerations
- 8. Pin Descriptions
- 9. Package Dimensions
- 10. Ordering Information
- 11. Environmental, Manufacturing, & Handling Information
- 12. Revision History