Cirrus Logic CS8952 - Manual (Page 43)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 43
DS206F1
5 Auto-Neg Complete Read/Write 0 When set, an interrupt will be generated once auto-
negotiation has completed successfully.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
4 Parallel Detection
Fault Read/Write 0 When set, an interrupt will be generated if auto-nego-
tiation determines that unstable legacy link signaling
was received.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
3 Parallel Fail Read/Write 0 When set, an interrupt will be generated when paral-
lel detection has occurred for a technology that is not
currently advertised by the local device.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
2 Remote Fault Read/Write 0 When set, an interrupt will be generated if a remote
fault condition is detected either by auto-negotiation
or by the Far-End Fault Detect state machine.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
1 Page Received Read/Write 0 When set, an interrupt is generated each time a page
is received during auto-negotiation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
0 Reserved Read Only 0
BIT NAME TYPE RESET DESCRIPTION