Cirrus Logic AN83 - Manual (Page 9)

AN83
AN83REV3 9
long as the CS8900A contains frames completely
received. If ‘n’ words are to be transferred from the
CS8900A to the system RAM, the DRQ signal re-
mains active until the (n-1)
th
word is transferred. If
the DMABurst is set, then the CS8900A deasserts
DRQ signal for 1.3 µs after every 28 µs. This op-
tion is provided so that in a system where multiple
DMA channels are operational, the DMA used for
the CS8900A will not take over the system bus for
long periods of time.
Selection of I/O, Memory and DMA Modes
The CS8900A always responds to all IO-mode re-
quests. After any reset, the CS8900A responds to
default IO base address of 0300h. However, this
default IO address can be changed by writing a dif-
ferent base address into a EEPROM connected to
the CS8900A. After any reset, the CS8900A reads
the contents of the EEPROM. If the EEPROM is
found valid, then the information in the EEPROM
is used by the CS8900A to program its internal reg-
isters.
Memory mode in the CS8900A can be enabled by
programming a proper base-address value in the
Memory Base Address register and setting the
MemoryE bit. Enabling of the memory mode can
be done by software or through an EEPROM con-
nected to the CS8900A.
In an IO mode, the CS8900A takes the minimum
space (16 bytes) in the system address space. For
systems where the address space limited, the IO
mode is a proper choice.
In the memory mode the CS8900A occupies 4K of
the address space. The software can access any of
the internal registers of the CS8900A directly. This
reduces accesses to the CS8900A by half when ac-
cessing registers.
In a system design, even if CS8900A is used in the
memory mode, the designer should make provi-
sions for accessing the CS8900A in the IO mode.
This dual-mode access has two advantages.
1) If an EEPROM is not used in the Ethernet de-
sign, the application can address the CS8900A
in IO mode (0300h) in order to enable memory
mode.
2) When the EEPROM is used, the EEPROM is
usually blank when a board is manufactured.
The CS8900A must be accessed in IO mode in
order to program the EEPROM.
Use of DMA for receive is efficient in a multi-task-
ing environment where the CPU could be busy ser-
vicing several higher priority tasks before it can
service receive frames off the Ethernet wire.
Design Example: CS8900A Interface to
MC68302
In this example the CS8900A is connected to Mo-
torola micro-controller MC68302. Please refer to
Figure 3 to check the connection of control signals
between CS8900A and Motorola’s micro-control-
ler MC68302.
Address Generation
The MC68302 has address decode generation logic
internal to the micro-controller. It generates chip
select signals such as CS1. In this example the CS1
is used to access the CS8900A in IO as well as in
Memory mode. The behavior of the CS1 signal
from the MC68302 is governed by values pro-
grammed in the CS1 base address register and the
CS1 option register. For example, if the CS1 base
address register is programmed as 3A01h, the CS1
will have a base address of D00xxxh. The CS1 op-
eration register controls the address range, number
of wait states (to be inserted automatically), etc. It
is recommended that the CS8900A be assigned 8K
of address space (0D00000h-0D01FFFh). Memo-
ry mode of the CS8900A is enabled with the mem-
ory base address register with a value 001000h.
The address line A12 separates IO address space
and memory address space. When A12 is low, the
CS8900A is accessed in an IO mode and when A12
is high, the CS8900A is accessed in memory mode.