Cirrus Logic AN83 - Manual (Page 8)

AN83
8 AN83REV3
ISA Bus
An ISA bus is a simple, asynchronous bus that can
easily be made to interface to most synchronous or
asynchronous buses. An ISA bus has separate ad-
dress and data lines as well as separate control lines
for read and write. ISA supports IO address space
of 64K bytes and Memory address space 32 Mega
bytes.
CS8900A in I/O Mode
When the CS8900A is used in an IO mode, it re-
sponds in the IO address space of the ISA. The
CS8900A responds to an IO access when
- Either of the bus IO command lines (IOR or
IOW) is active,
- The address on bus signals SA[0:15] matches
the address in the CS8900A IO base address
register, and
- Bus signals AEN, REFRESH, TEST, SLEEP
and RESET are inactive.
All other control signals are ignored for the IO op-
eration.
In an IO mode, the CS8900A uses 16 bytes of IO
address space. The address map for this mode is
described in Table 4.5 in the CS8900A datasheet.
CS8900A in Memory Mode
When the CS8900A is used in memory mode, the
CS8900A responds in the memory address space of
the ISA bus. The CS8900A responds to a memory
mode access when
- The CHIPSEL pin is active,
- Either of the bus memory command lines
(MEMR or MEMW) is active,
- Both of the IO command lines (IOR and IOW)
are inactive,
- the address on bus signals SA[0:19] matches
the address in the CS8900A’s Memory Base
address register,
- MemoryE (Bit A) in the CS8900A’s BusCTL
(Register 17) is active and,
- Bus signals AEN, REFRESH, TEST, SLEEP
and RESET are inactive.
In memory mode, all the internal registers of the
CS8900A can be accessed directly via memory
reads/writes. Please refer to the CS8900A
datasheet for the memory address map.
DMA Interface of the CS8900A
The CS8900A can interface to an external 16-bit
DMA channel for receive operations. A DMA-
mode receive operation can be selected by setting
either RxDMAOnly (bit 9) or AutoRxDMA (bit
10) in the CS8900A’s RxCFG (Register 3) register.
The CS8900A will request services of an external
DMA after a receive frame is accepted by the
CS8900A, completely received and stored in on
chip RAM of the CS8900A. The CS8900A gener-
ates a request for DMA access (DRQx) signal when
it has at least one receive frame that can be trans-
ferred to the system memory. The external DMA
channel should assert DMACK signal when it is
ready to transfer data. The DMA controller gener-
ates address for the system memory and asserts the
AEN signal. When DMACK and AEN signals are
asserted, the CS8900A provides 16 bits of frame
data for every pulse of the IOR signal. Notice that
the CS8900A ignores address on the SA address
lines for this operation. In this way the CS8900A
supports “direct mode” of operation of DMA. In
direct mode, the external DMA controller gener-
ates addresses for the system RAM, and generates
the appropriate control signals for the RAM and IO
device. The data moves directly from the IO device
to the RAM. In the case of the CS8900A, the DMA
controller generates a write signal for RAM and a
read signal for the CS8900A. The data flows di-
rectly from the CS8900A to the system RAM. The
direct mode of DMA operation is 100% more effi-
cient than typical read-followed-by-write DMA
operation.
The length of time that the CS8900A holds the
DRQ signal active depends upon the DMABurst
(bit B) bit of the BusCTL (Register 17) register. If
the DMABurst is clear, the DRQ remains active as