Cirrus Logic AN83 User Manual
Cirrus Logic Hardware
1
Copyright
Cirrus Logic, Inc. 2001
(All Rights Reserved)
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
AN83
Application Note
&U\VWDO /$1 CS8900A ETHERNET CONTROLLER
TECHNICAL REFERENCE MANUAL
By Deva Bodas
Revised by James Ayres
JUN ‘01
AN83REV3
Table of contents
Document Outline
- Crystal lan™ cs8900a ethernet controller technical reference manual
- Schematic Checklist
- software checklist
- INTRODUCTION TO CS8900A TECHNICAL REFERENCE MANUAL
- HARDWARE DESIGN
- CS8900A: Connecting to NON-ISA bus SYSTEMS
- The CS8900A Architecture
- Selection of I/O, Memory and DMA Modes
- Design Example: CS8900A Interface to MC68302
- Databus (SD[0:15]) Connection
- Checklist for Signal Connections to the CS8900A
- EEPROM Optional
- Design Example: CS8900A Interface to Cirrus Logic CL-PS7211
- Design Example: CS8900A Interface to Hitachi SH3
- Summary
- Ethernet Hardware Design for Embedded Systems and Motherboards
- Low Cost Ethernet Combo Card Reference Design: CRD8900
- General Description
- Board Design
- Figure 12. Placement of Components
- Figure 13. CS8900A Schematic (Combo Card Application)
- Figure 14. Power Supply Decoupling Schematic
- Figure 15. Boot PROM Schematic
- Figure 16. AUI Schematic
- Figure 17. 10BASE-2 Schematic
- Figure 18. PAL Decode of LA[20-23]
- Crystal Oscillator
- ISA Bus Interface
- External Decode Logic
- EEPROM
- Socket for Optional Boot PROM
- Table 2. BootPROM Descriptions Stored in CS8900A PacketPage
- LEDs
- 10BASE-T Interface
- AUI Interface
- 10BASE-2 Interface
- Logic Schematics
- Component Placement and Routing of Signals
- Bill of Material
- Addressing the CS8900A: I/O Mode, Memory Mode
- Layout Considerations for the CS8900A
- General Guidelines
- Power Supply Connections
- Two Layered Printed Circuit Board (PCB)
- Multi-layered Printed Circuit Board
- Figure 25. Placement of Components, Top Side
- Figure 26. Placement of Components, Solder Side
- Figure 27. Component (top) side of four-layer board
- Figure 28. +5V Plane of four-layer board
- Figure 29. Ground Plane of four-layer board
- Figure 30. Solder side (bottom) of four-layer board
- Figure 31. Placement of Decoupling Capacitor (Bottom side, under CS8900A)
- Figure 32. Routing of Decoupling Capacitor (Top side, component side)
- Routing of the Digital Signals
- Routing of the Analog Signals
- Recommended Magnetics for the CS8900A
- JUMPERLESS DESIGN
- Obtaining IEEE Addresses
- DEVICE DRIVERS AND SETUP/INSTALLATION SOFTWARE
- CONTACTING CUSTOMER SUPPORT AT Cirrus