Cirrus Logic AN83 - Manual (Page 15)

AN83
AN83REV3 15
ETHERNET HARDWARE DESIGN FOR
EMBEDDED SYSTEMS AND
MOTHERBOARDS
This section describes the hardware design of a
four-layer, 10BASE-T solution intended for use on
PC motherboards, or in other embedded applica-
tions. The goal of this design is minimal board
space and minimal material cost. Therefore, a num-
ber of features (BootPROM, AUI, 10BASE-2) are
not supported in this particular PCB design. An ex-
ample of this circuit is included in this technical
reference manual, and is implemented in an ISA
form factor. This same circuit can be implemented
directly on the processor PCB.
General Description
The small footprint, high performance and low cost
of the CS8900A Ethernet solution, makes the
CS8900A an ideal choice for embedded systems
like personal computer (PC) mother boards. The
very high level of integration in the CS8900A re-
sults in a very low component count Ethernet de-
sign. This makes it possible to have a complete
solution fit in an area of 1.5 square inches.
Board Design Considerations
Crystal Oscillator
The CS8900A, in this reference design, uses a
20.000 MHz crystal oscillator. The CS8900A has
internal loading capacitance of 18pF on the
XTAL1 and XTAL2 pins. No external loading ca-
pacitors are needed. Please note that the crystal
must be placed very close to XTL1 and XTL2 pins
of the CS8900A.
This crystal oscillator can be eliminated if accurate
clock signal (20.00 MHz ±0.01% and 45-55 duty
cycle) available in the system.
ISA Bus Interface
The CS8900A has a direct ISA bus interface. Note
that the ISA bus interface is simple enough to allow
the CS8900A to interface with variety of micro-
processors directly or with the help of simple pro-
grammable logic like a PAL or a GAL.
This reference design uses the ISA adapter card
form factor. All the ISA bus connections from the
CS8900A are directly routed to the ISA connector.
The pin-out of the CS8900A is such that if the
CS8900A is placed as shown in Figures 6 and 7,
there will be almost no cross-over of the ISA sig-
nals.
External Decode Logic
The CS8900A can be accessed in I/O mode or
memory mode. For this reference design, in mem-
ory mode the CS8900A is in the conventional or
upper memory of the PC. That is, it resides in the
lower 1 Mega bytes of address space.
To use the CS8900A in extended memory address
space requires an external address decoder. This
decoder decodes upper 4 bits (LA[20:23]) of 24 bit
ISA address lines. In many embedded micropro-
cessors such decodes are available though the mi-
croprocessors itself.
Please refer to “Extended Memory Mode” on
page 31 for further information.
EEPROM
A 64 word (64 X16 bit) EEPROM (location U3) is
used in the reference design to interface with the
CS8900A. This EEPROM holds the IEEE as-
signed Ethernet MAC (physical) address for the-
board (see “Obtaining IEEE Addresses” on
page 55). The EEPROM also holds other configu-
ration information for the CS8900A. The last few
bytes of the EEPROM are used to store information
about the hardware configuration and software re-
quirements.
In an embedded system, such as a PC, the system
CMOS RAM or any other non-volatile memory
can be used to store the IEEE address and Ethernet
configuration information. In such a case an EE-