Cirrus Logic AN83 - Manual (Page 31)

AN83
AN83REV3 31
Memory Mode
In the memory mode, there are two options where
the CS8900A can be placed in the ISA memory ad-
dress map, lower memory (below 1 Meg) or ex-
tended memory (above 1 Meg). The lower
memory typically consists of the conventional
memory (up to 640K) and upper memory (640K to
1 Meg. boundary). To access anything in extended
memory, the processor (386 and above) is used in
the “Enhanced Mode”.
The CS8900A will respond to IO addresses pro-
grammed in its IO Base Address Register (Packet
Page Base + 020h) even if memory mode is en-
abled. To enable memory mode, first write a prop-
er 20 bit value to Memory Base Address register at
Packet page base + 02Ch & 02Eh. Then set Mem-
oryE (bit 0Ah) in the Bus CTL register (Register
17) to one.
These operations can be performed either by doing
writes using IO mode accesses or using an EE-
PROM as described in Sections 3.4 and 3.5 of the
CS8900A datasheet. The CS8900A will respond
to an ISA memory access, if the CHIPSEL pin is
active (LOW), and the SA[19:0] match the value
stored in Memory Base Address Registers. The
lower 12 bits of the address lines are always ig-
nored. This dictates that the CS8900A must always
be placed at a 4K boundary in the ISA memory ad-
dress space.
Lower Memory Mode
To use a CS8900A in the lower 1 Meg address
space, SMEMRD and SMEMWR lines from the
ISA bus are connected to MEMR and MEMW pins
of CS8900A respectively. The SMEMRD and
SMEMWR signals become active only for the low-
er 1 Meg of the ISA address space. The CHIPSEL
pin of the CS8900A should be connected to
ground.
Extended Memory Mode
The CS8900A can also be mapped in to the extend-
ed memory of a Personal Computer (PC) system.
This provides flexibility and more options when
several components are installed in a PC with
CS8900A based network cards.
To address the CS8900A in extended memory
mode, the processor is used in an enhanced mode.
In an enhanced mode, 24 bits of ISA address lines
are used for address generation. Since the
CS8900A accepts 20 bits of address lines, an exter-
nal address decoder circuit is required to decode the
4 upper address bits. The CS8900A has interface
pins for external decoder circuit.
This arrangement makes provisions so that the
CS8900A can be placed anywhere in the extended
memory address map as long as it is at a 4K address
boundary. The MEMR and MEMW signals of the
ISA bus are active for any ISA memory space ac-
cess, therefore, for extended memory mode opera-
tion, these signals are connected to the MEMR and
MEMW pins of the CS8900A respectively.
The external address decoder circuit consists of a
single and simple Programmable Array Logic like
a 16R4 or GAL16V8. Please refer to the schematic
shown in Figure 21 as an example of such a decod-
er circuit. The PAL16R4 has 4 registers Q[23:20].
These registers are programmed by the serial input
via the inputs EESK (clock), ELCS (enable pin)
and EEDataOut (serial data out). This decoder
compares the 4 upper address bits, namely
LA[23:20], with the internal programmable regis-
ter, Q[23:20]. Before memory mode of the
CS8900A is enabled, Q[23:20] must be initialized
to a proper value.
In the design example, Q[23:20] form a left shift
register. The ELCS pin of the CS8900A is used in-
conjunction with EESK and EEDataOut pins to
shift in the data for Q[23:20] serially. To program
a value, set the ELSEL bit (bit A in Packet Page
base + 040h) to HIGH. Then the EEPROM inter-