Cirrus Logic AN83 - Manual (Page 27)

AN83
AN83REV3 27
10BASE-2 Interface
A 10BASE-2 transceiver IC, the 83C92C, is used
to generate a 10BASE-2 interface for the reference
design. Please refer to Figure 17 for details about
the components and connection.
A 12 volt to -9 volt DC to DC voltage converter (lo-
cation U5) is used to generate an isolated -9 volt
supply for the 83C92C. The DC-DC converter
used in the reference design has an enable pin. This
enable pin is connected to the HC1 pin of the
CS8900A. Usually the DC-DC converter is dis-
abled when the 10BASE-2 interface is not used.
This not only reduces power used by the adapter
card but also eliminates any noise the 10BASE-2
circuitry can induce on the 10BASE-T or AUI in-
terface that may be in use. This reference design
uses a “low” enable DC-DC converter. That is, the
DC-DC converter is enabled when the enable pin is
logic low. However, the board can be built with a
“high” enable DC-DC converter. In such a case,
software that controls the enable and disable oper-
ations of the DC-DC converter should be modified.
An optional method is to use an integrated module
that includes all the needed 10Base2 components.
Contact Halo Electronics for information on their
TnT integrated 10Base2 modules.
Logic Schematics
Figures 10 and 13 through 17 detail logic schemat-
ics for the various circuits used in the reference de-
sign.
Component Placement and Routing of Sig-
nals
Figure 12 shows the component placement used for
the reference design. Figure 19 shows the routing
of signals on the component side of the printed cir-
cuit board (PCB) while Figure 20 shows routing on
the solder side. Please refer to “Layout Consider-
ations for the CS8900A” on page 35 of this docu-
ment for an explanation and information about
placement of components on the board.
Bill of Material
Table 3 contains a list of components that are typi-
cally used to assemble this adapter card. For most
of the components, there are several alternative
manufacturers.
Addressing the CS8900A: I/O Mode,
Memory Mode
The CS8900A, integrated Ethernet controller, has
20 address pins that directly connect to SA[19:0] of
the ISA bus. The CS8900A has an internal address
comparator to compare the ISA address with its
base address registers.
I/O Mode
In IO mode, the lower 16 bits of the ISA address are
compared with the address stored in IO Base Ad-
dress register (Packet Page base + 020h). When an
address match occurs and one of the IO command
(IOR or IOW) lines is active, the CS8900A re-
sponds to that IO access. The lower 4 bits of ad-
dress lines are ignored by the address comparator.
This dictates that the CS8900A must always be at a
16 byte address boundary of the ISA IO address
space. The pin CHIPSEL is ignored for an IO mode
access.
After RESET the CS8900A responds to IO address
0300h. However, this condition can be modified
with use of an EEPROM or by software. Immedi-
ately after a reset, the CS8900A reads the EE-
PROM interfaced to it. If the EEPROM has valid
data (valid start data and correct checksum), it will
read information stored in the EEPROM to initial-
ize its own registers including the IO base address
register. Please refer to the CS8900A datasheet for
details about EEPROM configuration and pro-
gramming. A CS8900A will always respond to val-
id IO address (even if its memory mode is enabled).