Cirrus Logic AN83 - Manual (Page 21)

AN83
AN83REV3 21
LOW COST ETHERNET COMBO CARD
REFERENCE DESIGN: CRD8900
This section describes the hardware design of a low-
cost, two-layer, full-featured Ethernet solution in-
tended for use in PC ISA-bus. The goal of this design
is a high degree of application flexibility. Therefore,
a number of features (BootPROM, AUI, 10BASE-2)
are supported. An example of this circuit is included
in this Technical Reference Manual.
General Description
The CS8900A ISA Ethernet controller is used in
this low cost, high performance ISA Ethernet
adapter card. This card has AUI, 10BASE-T and
10BASE-2 interfaces. The very high level of inte-
gration of the CS8900A results in a very low com-
ponent count. This makes it possible to design a
half height, two layered 16 bit ISA Ethernet adapter
card. Since the analog filters are integrated on the
CS8900A, the card may be compliant with FCC
part 15 class (B) compliant.
Board Design
A recommended component placement is shown in
Figure 12, and a recommended board schematics
are shown in Figures 10 and 13 through 17.
Crystal Oscillator
The CS8900A, in the reference design, uses a
20.000 MHz crystal oscillator. Please note that the
crystal must be placed very close to XTL1 and
XTL2 pins of the CS8900A.
ISA Bus Interface
The ISA bus connections from the CS8900A can be
easily routed to the ISA connector. If the pin-out of
the CS8900A is placed as shown in Figure 12, there
will be almost no cross-over of the ISA signals. It
is also important to provide very clean and ade-
quate +5 V and ground connections to the
CS8900A.
External Decode Logic
The CS8900A can be accessed in both I/O and
memory modes. The CS8900A internally decodes
the SA[0:19] address lines for the lower 1 M of
memory. The reference design uses an external de-
code logic to allow the card to also decode decodes
the upper 4 bits of the ISA address (LA[23:20]),
thus allowing the CS8900A to reside anywhere in
extended memory. This decode logic is implement-
ed using a 16R4 PAL at location U4. This logic is
configured by the CS8900A. The PAL then de-
codes the upper 4 bits of the ISA address. Please re-
fer to “Addressing the CS8900A: I/O Mode,
Memory Mode” on page 27 of this document for
further information.
EEPROM
A 64 word (64 X16) EEPROM (location U3) is
used in the reference design to interface with the
CS8900A. This EEPROM holds the IEEE as-
signed Ethernet MAC (physical) address for the
board. (see “Embedded Designs” on page 54) The
EEPROM also holds other configuration informa-
tion for the CS8900A. The last few bytes of the
EEPROM are used to store information about the
hardware configuration and software requirements.
Please refer to the CS8900A datasheet for informa-
tion about programming the EEPROM. Please re-
fer to “JUMPERLESS DESIGN” on page 45 of
this document for information about EEPROM in-
ternal word assignment.
Socket for Optional Boot PROM
A socket is provided at location U6 for the optional
Boot PROM. This Boot PROM is required in sys-
tems that require remote boot capability, for exam-
ple diskless work stations. The 74LS245 data
buffer at U7 is provided for the Boot PROM (See
Figure 15). Inside the CS8900A there are registers
that hold the Boot PROM base address (Pack-
etPage base + 030h) and the Boot PROM address
mask (PacketPage base + 034h). A 20 bit address