An83 – Cirrus Logic AN83 User Manual
Page 33
AN83
AN83REV3
33
Figure 23 shows a simple PALASMTM program
for the 16R4 PAL that is used in the design shown
in Figure 21.
;PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE
High address decoder PATTERN
REVISION
AUTHOR
Deva Bodas
COMPANY
Crystal Semiconductor
DATE
04/01/1994
CHIP
_decoder
PAL16R4
;--------------------------------- PIN Declarations ---------------
PIN
1
SCLK
; Serial clock from the CS8900A pin 4 (EESK)
PIN
2
CS_EL_b
; External Logic enable from the CS8900A pin 2 (ELCS*)
PIN
3
SDATA
; Serial data in from the CS8900A pin 5 (EEDataOut)
PIN
4
ALE
; Address latch enable from the ISA bus
PIN
5
LA23
; Address 23
PIN
6
LA22
; Address 22
PIN
7
LA21
; Address 21
PIN
8
LA20
; Address 20
PIN
9
RESET
; ISA reset pin
PIN
11
OE
; Output enable for the registered outputs
PIN
12
ADD_VALID
COMB
; When high, Q[23:20] are programmed
PIN
13
EQUALH
COMB
; Upper 2 bits of address match
PIN
19
EQUALL
COMB
; Lower 2 bits of address match
PIN
18
CHIPSEL_b
COMB
; CHIPSEL to the CS8900A pin 7
PIN
14
Q20
; REG
PIN
15
Q21
; REG
PIN
16
Q22
; REG
PIN
17
Q23
; REG
;----------------------------------- Boolean Equation Segment ------
EQUATIONS
; Serial shift register
; When CS_EL_b is inactive (1), no change
; When CS_EL_b is active (0), shift in data