Cirrus Logic CS5461A - Manual (Page 26)

CS5461A
26 DS661F3
6. REGISTER DESCRIPTION
1. “Default” => bit status after power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Configuration Register
Address: 0
Default = 0x000001
PC[6:0] Phase compensation. A 2’s complement number which sets a delay in the voltage channel rel-
ative to the current channel. When MCLK = 4.096 MHz and K = 1, the phase adjustment range
is approximately
2.8 degrees with each step approximately 0.04 degrees (assuming a power
line frequency of 60 Hz). If (MCLK/K) is not 4.096 MHz, the values for the range and step size
should be scaled by the factor 4.096 MHz / (MCLK/K). Default setting is 0000000 = 0.0215 de-
gree phase delay at 60 Hz (when MCLK = 4.096 MHz).
Igain Sets the gain of the current PGA.
0 = Gain is 10x (default)
1 = Gain is 50x
EWA Allows the E1 and E2 pins to be configured as open-collector output pins.
0 = Normal outputs (default)
1 = Only the pull-down device of the E1 and E2 pins are active
IMODE, IINV Interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = Active-low level (default)
01 = Active-high level
10 = High-to-low pulse
11 = Low-to-high pulse
EPP Allows the E1 and E2 pins to be controlled by the EOP and EDP bits.
0 = Normal operation of the E1 and E2 pins. (default)
1 = EOP and EDP bits defines the E1 and E2 pins.
EOP EOP defines the value of the E1 pin when EPP = 1.
0 = Logic level low (default)
EDP EDP defines the value of the E2 pin when EPP = 1.
0 = Logic level low (default)
ALT Alternate pulse format, E1 and E2 becomes active low alternating pulses with an output fre-
quency proportional to the active power.
0 = Normal (default), Mechanical Counter or Stepper Motor Format
1 = Alternate Pulse Format, also MECH = 1
VHPF (IHPF) Enables the high-pass filter on the voltage (current) channel.
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
23 22 21 20 19 18 17 16
PC6 PC5 PC4 PC3 PC2 PC1 PC0 Igain
15 14 13 12 11 10 9 8
EWA IMODE IINV EPP EOP EDP
7 6 5 4 3 2 1 0
ALT VHPF IHPF iCPU K3 K2 K1 K0