Cirrus Logic CRD49530-USB - Manual (Page 34)

5-1 Copyright 2008 Cirrus Logic DS705RD3
Introduction
CRD49530-USB User’s Manual
Chapter 5
CRD49530-USB Schematics
5.1 Introduction
The schematics included in this document are the original Revision A schematics of the CRD49530 and
reflect the board as it was manufactured. Newer schematics may be available which incorporate feature
additions or corrections, and may not reflect Rev. A hardware.
5.2 Detailed Schematic Descriptions
5.2.1 CS49530-USB Block Diagram
Figure 5-1 shows the CRD49530-USB block diagram.
5.2.2 CS4953xx DSP
The schematic for the CS4953xx core is shown in Figure 5-2 . The DSP core is driven by an external
crystal circuit. This fixed 24.576 MHz clock is buffered and driven out the XTAL_OUT pin of the CS4953xx
chip and can be used as the audio MCLK for analog sampling in the CS42448 codec.
The PLL filter circuit on the CRD49530 is designed to allow the use of the CS4953xx family of DSPs and
the legacy CS495xx DSPs. The board is configured for the CS4953xx PLL by default, but extra
components can be populated to support the CS495xx as explained by the note on the bottom of the
schematic page.
The DSP has a dedicated reset line (DSP_RESET) that must be driven by the host to initialize the
CS4953xx’s communication mode and initiate the first boot sequence. This signal is independent of any
other reset on the board and can be used to sequence device power up.
The host communication protocol of the DSP is determined by the state of the HS[3:0] pins at the rising
edge of reset. The communication mode for the CRD49530 is slave-I 2 C when the SPI_MODE_SEL signal
is driven low, and slave-SPI when the SPI_MODE_SEL pin is driven high.
The serial host control port (SCP1_CLK, SCP1_MOSI, SCP1_MISO/SDA, SCP1_CS, SCP1_IRQ,
SCP1_BSY) is used by the host controller to boot and control the DSP. Note that the pull-up resistors on
the SCP1_IRQ and SCP1_BSY pins are required for both SPI and I
2
C control, since these are open-drain
pins. The pull-ups on the SCP1_CLK and SCP1_SDA pins are required only for I
2
C operation.
The second serial control port (SCP2CK, SCP2_MOSI, SCP2_MISO, EE_CS) is connected to the on-
board serial SPI flash chip found on the memory page of the schematic.
The DSP has a debug port (DBDA, DBCK) that allows a developer to debug the DSP during normal
operation. This is a slave port that can be connected to an I
2
C master, or it can be simply terminated with
pull-up resistors.
The audio input pins of the CS4953xx are driven by a multiplexer (U1, U2) that chooses between I
2
S
audio from an off-board source (HDMI audio) and the on-board S/PDIF RX (CS8416) and audio codec
(CS42448). This multiplexer defaults to choose the on-board audio sources. The HDMI audio delivery
interface is currently under development.