Advanced ecc population guidelines, Online spare population guidelines, Lockstep memory population guidelines – HP ProLiant DL160 Gen8 Server User Manual
Page 50
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Hardware options installation 50
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White DIMM slots denote the first slot of a channel (Ch 1-A, Ch 2-B, Ch 3-C, Ch 4-D).
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Do not mix LRDIMMs, UDIMMs, or RDIMMs.
•
Do not install more than two UDIMMs per channel. UDIMMs should not be installed in slots Ch 1-I, Ch
2-J, Ch 3-K, or Ch 4-L.
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When two processors are installed, install the DIMMs in sequential alphabetical order balanced
between the two processors: P1-A, P2-A, P1-B, P2-B, P1-C, P2-C, and so on.
For detailed memory configuration rules and guidelines, use the Online DDR3 Memory Configuration Tool
on the HP website
DIMM speeds are supported as indicated in the following table.
Populated slots
(per channel)
Rank
Speeds supported (MT/s)
1
Single- or dual-rank
1333, 1600
1
Quad-rank
1333
2
Single- or dual-rank
1333
3
Single- or dual-rank
1066
Advanced ECC population guidelines
For Advanced ECC mode configurations, observe the following guidelines:
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Observe the general DIMM slot population guidelines (on page
•
DIMMs may be installed individually.
Online Spare population guidelines
For Online Spare memory mode configurations, observe the following guidelines:
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Observe the general DIMM slot population guidelines (on page
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Each channel must have a valid online spare configuration.
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Each channel can have a different valid online spare configuration.
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Each populated channel must have a spare rank:
o
A single dual-rank DIMM is not a valid configuration.
o
LRDIMMs are treated as dual-rank DIMMs.
Lockstep Memory population guidelines
For Lockstep memory mode configurations, observe the following guidelines:
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Observe the general DIMM slot population guidelines (on page
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DIMM configuration on all channels of a processor must be identical.
•
In multi-processor configurations, each processor must have a valid Lockstep Memory configuration.
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In multi-processor configurations, each processor may have a different valid Lockstep Memory
configuration.