Atec Anritsu-MT8212E-MT8213E - Manual (Page 19)

Cell Master™ MT8212E and MT8213E Specifications
MT8212E and MT8213E TDS PN: 11410-00485 Rev. M 19 of 32
Backhaul Analyzers (Options 0051, 0052, 0053)
T1 Bit-Error-Rate Tester (BERT) (Option 0051)
Measurements
Error Detection Frame Bits, Bit Errors, BER, BPV, CRC, PATLS
Error Analysis (ITU G-821) Errored Seconds (ES), Error Free Seconds (EFS), Severely Errored Seconds (SES), Unavailable Seconds
(UAS), Available Seconds (AS), Degraded Minutes (DGRM)
Rx Signal Frequency (± 5 ppm, Max/Min), Vpp (± 5%) (Max/Min), dBdsx, Clock Slips, Frame Slips
VF Frequency (100 Hz to 3000 Hz, ± 3 Hz), Power (–40.0 dBm to +3.0 dBm, ± 0.2 dBm)
Status (Historical and Current) Rx (Signal, Frame Sync, Pattern Sync), DS1 (Alarms, Errors, B8ZS)
Status (Current) Tx (Alarm On, Error On, Loop On)
Setup
BERT Display Table, Histogram, Event List, Clear History
VF Tx (Off/On), Channel (1-24), Tx Freq, Tx Level (–30 dBm to 0 dBm), Volume, Audio, Clear
Line Code AMI, B8ZS
Tx Clock Internal (1.544 MHz ± 5 ppm), Recovered, External
Tx LBO 0.0 dB, –7.5 dB, –15.0 dB
Rx Input Terminate (Bantam connector 100 Ω balanced)
Monitor (Connect via 20 dB pad in DSX, 20 dB flat gain)
Bridge (≥ 1000 Ω, –36 dB to +6 dB)
Framing ESF, SF-D4
Payload T1 (1.544 Mbps), Fractional T1 (Nx64, 64, 56, 16, 8 kbps)
Pulse Shapes Conform to ANSI T1.403 and ITU G.703
Patterns QRSS, PRBS (2-9, 2-11, 2-15, 2-20, 2-23), All Ones, All Zeros, 1-in-8 (1-in-7), 2-in-8, 3-in-24 T1 Daly,
Six User defined (≤ 32 bits), Inverse Patterns (On/Off), Remote Loop Up/Down
Loop Codes CSU, NIU, Link Type (In-Band, Data-Link), Self Loop Up/Down, Loop Code User Defined
Error Insertion Bit Error, Bit Error Rate (BER), BPV, Frame Bit Error, Error (On/Off)
Alarm Insertion AIS On/Off (Blue Alarm), RAI On/Off (Yellow Alarm)
Data Log 1 minute to 3 days
E1 Bit-Error-Rate Tester (BERT) (Option 0052)
Measurements
Error Detection Frame Bits, Bit Errors, BER, BPV, CRC, E Bits
Error Analysis (ITU G-821) Errored Seconds (ES), Error Free Seconds (EFS), Severely Errored Seconds (SES),
Unavailable Seconds (UAS), Available Seconds (AS), Degraded Minutes (DGRM)
Rx Signal Frequency (± 5 ppm, Max/Min), Vpp (± 5%) (Max/Min), dBdsx, Clock Slips, Frame Slips
VF Frequency (100 Hz to 3000 Hz), Power (–40.0 dBm to +3.0 dBm, ± 0.2 dBm)
Status (Historical and Current) Rx (Signal, FAS, Pattern Sync), E1 (Alarms, Errors)
Status (Current) Tx (Alarm On, Error On)
Setup
BERT Display Table, Histogram, Event List, Clear History
VF Tx (Off/On), Channel (1 to 31), Tx Freq, Tx Level (–30 dBm to 0 dBm), Volume, Audio, Clear
Line Code AMI, HDB3
Tx Clock Internal (2.048 MHz ± 5 ppm), Recovered, External
Rx Input Terminate (RJ48 120/75 Ω balanced, BNC 75 Ω unbalanced, –43 dB to +6 dB),
Bridge (≥ 1000 Ω, –43 dB to +6 dB)
Monitor (Connect via 20 dB pad in DSX, 20 dB flat gain)
Framing PCM30, PCM30 CRC-4, PCM31, PCM31 CRC-4
Payload E1 (2.048 Mbps), Fractional E1 (N x 64, 64, 16, 8 kbps)
Pulse Shapes Conform to ITU G.703
Patterns QRSS, PRBS (2-9, 2-11, 2-15, 2-20, 2-23), All Ones, All Zeros, 1010, 1-in-8 (1-in-7), 2-in-8, 3-in-24,
Six User defined (≤ 32 bits), Inverse Patterns (On/Off)
Loopback Mode Self loop
Error Insertion Bit Error, Bit Error Rate (BER), Frame Bit Error, Error (On/Off)
Alarm Insertion AIS (On/Off) (Blue Alarm), RAI (On/Off) (Yellow Alarm)
Data Log 1 minute to 3 days