Rainbow Electronics ATA6834 - Manual (Page 8)

8
9122B–AUTO–10/08
ATA6833/ATA6834 [Preliminary]
3.4 Reset and Watchdog Management
The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time T
OSC
is determined by the external resistor R
WD
. A HIGH signal on WDD pin enables the watchdog
function; a LOW signal disables it. Since WDD pin is equipped with an internal pull-up resistor
the watchdog is enabled by default. In order to keep the current consumption as low as possible
the watchdog is switched off during Sleep Mode.
The timing diagram in Figure 3-4 shows the watchdog and external reset timing.
Figure 3-4. Timing Diagram of the Watchdog in Conjunction with the /RESET Signal
After power-up of the VCC regulator (VCC output exceeds 88% of its nominal value) /RESET
output stays LOW for the timeout period t
res
(typical 10 ms). Subsequently /RESET output
switches to HIGH. During the following time t
d
(typical 500 ms) a rising edge at the input WD is
expected otherwise another external reset will be triggered.
When the watchdog has been correctly triggered for the first time, normal watch-dog operation
begins. A normal watchdog cycle consists of two time sections t
1
and t
2
followed by a short pulse
for the time t
resshort
at /RESET if no valid trigger has been applied at pin WD during t
2
. Rising
edges on WD pin during t
1
also cause a short pulse on /RESET. Start for such a cycle is always
the time of the last rising edge either on WD pin or on /RESET pin.
If the watchdog is disabled (WDD = LOW), only the initial reset for the time t
res
after power-up
will be generated.
Additional resets will be generated if the VCC output voltage drops below 80% of its nominal
value.
The following example demonstrates how to calculate the timing scheme for valid watchdog trig-
ger pulses, which the external microcontroller has to provide in order to prevent undesired
resets.
Watchdog
trigger edge
Reset and lead
time, no trigger Watchdog cycle,
no trigger
Watchdog cycle, trigger
during t
2
window
Reset and lead time,
trigger during lead time
t
resshort
t
1
t
2
t
1
t
d
t
res
t
d
t
1
t
res
t
2
Watchdog trigger
in t
2
window
88% VCC
VCC
WD
/RESET