Rainbow Electronics ADC08D1000 - Manual (Page 27)

2.0 Applications Information
(Continued)
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D1000 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
On-Command Calibration Section 2.4.2.2.
The internal power-on calibration circuitry comes up in a
random state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
2.4.2.2 On-Command Calibration
Calibration may be run at any time in NORMAL mode only.
Do not run a calibration whilst operating the ADC in Auto
DES Mode.
To Calibrate the device, bring the CAL pin high for a mini-
mum of 80 input clock cycles after it has been low for a
minimum of 80 input clock cycles. Holding the CAL pin high
upon power up will prevent execution of power-on calibration
until the CAL pin is low for a minimum of 80 input clock
cycles, then brought high for a minimum of another 80 input
clock cycles. The calibration cycle will begin 80 input clock
cycles after the CAL pin is thus brought high. The CalRun
signal should be monitored to determine when the calibra-
tion cycle has completed.
The minimum 80 input clock cycle sequences are required to
ensure that random noise does not cause a calibration to
begin when it is not desired. As mentioned in section 1.1 for
best performance, a self calibration should be performed 20
seconds or more after power up and repeated when the
ambient temperature changes more than 30˚C since the last
self calibration was run. SINAD drops about 1.5 dB for every
30˚C change in die temperature and ENOB drops about 0.25
bit for every 30˚C change in die temperature.
2.4.2.3 Calibration Delay
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in Section 1.1.1. The calibration delay values
allow the power supply to come up and stabilize before
calibration takes place. With no delay or insufficient delay,
calibration would begin before the power supply is stabilized
at its operating value and result in non-optimal calibration
coefficients. If the PD pin is high upon power-up, the calibra-
tion delay counter will be disabled until the PD pin is brought
low. Therefore, holding the PD pin high during power up will
further delay the start of the power-up calibration cycle. The
best setting of the CalDly pin depends upon the power-on
settling time of the power supply.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.3 Output Edge Synchronization
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the
rising edge or the falling edge of the DCLK signal, so that
either edge of that DCLK signal can be used to latch the
output data into the receiving circuit.
When OutEdge (pin 4) is high, the output data is synchro-
nized with (changes with) the rising edge of the DCLK+ (pin
82). When OutEdge is low, the output data is synchronized
with the falling edge of DCLK+.
At the very high speeds of which the ADC08D1000 is ca-
pable, slight differences in the lengths of the DCLK and data
lines can mean the difference between successful and erro-
neous data capture. The OutEdge pin is used to capture
data on the DCLK edge that best suits the application circuit
and layout.
2.4.4 LVDS Output Level Control
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
For short LVDS lines and low noise systems, satisfactory
performance may be realized with the OutV input low. If the
LVDS lines are long and/or the system in which the
ADC08D1000 is used is noisy, it may be necessary to tie the
OutV pin high.
2.4.5 Dual Edge Sampling
The Dual Edge Sampling (DES) feature causes one of the
two input pairs to be routed to both ADCs. The other input
pair is deactivated. One of the ADCs samples the input
signal on one input clock edge (duty cycle corrected), the
other samples the input signal on the other input clock edge
(duty cycle corrected). The result is a 4:1 demultiplexed
output with a sample rate that is twice the input clock fre-
quency.
To use this feature in the non-enhanced control mode, allow
pin 127 to float and the signal at the "I" channel input will be
sampled by both converters. The Calibration Delay will then
only be a short delay.
In the enhanced control mode, either input may be used for
dual edge sampling. See Section 1.1.5.1.
IMPORTANT NOTES :
1) For the Extended Control Mode - When using the Auto-
matic Clock Phase Control feature in dual edge sampling
mode, it is important that the automatic phase control is
disabled (set bit 14 of DES Enable register Dh to 0) before
the ADC is powered up. Not doing so may cause the device
not to wakeup from the powerdown state.
2) For the Non-Extended Control Mode - When the
ADC08D1000 is powered up and DES mode is required,
ensure that pin 127 (CalDly/DES/notSCS) is initially pulled
low during or after the power up sequence. The pin can then
be allowed to float or be tied to VCC/2 to enter the DES
mode. This will ensure that the part enters the DES mode
correctly.
3) The automatic phase control should also be disabled if the
input clock is intrerrupted or stopped for any reason.This is
also the case if a large abrupt change in the clock frequency
occurs.
4) If a calibration of the ADC is required in Auto DES mode,
the device must be returned to the Normal Mode of operation
before performing a calibration cycle. Once the Calibration
has been completed, the device can be returned to the Auto
DES mode and operation can resume.
ADC08D1000
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