Rainbow Electronics ATtiny15L - Manual (Page 5)

5
ATtiny15L
1187E–AVR–06/02
ATtiny15L
Architectural
Overview
The fast-access Register File concept contains 32 x 8-bit general purpose working reg-
isters with a single-clock-cycle access time. This means that during one single clock
cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output
from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This
pointer is called the Z-pointer, and can address the Register File, IO file and the Flash
Program memory.
Figure 2. The ATtiny15L AVR RISC Architecture
The ALU supports arithmetic and logic functions between registers or between a con-
stant and a register. Single-register operations are also executed in the ALU. Figure 2
shows the ATtiny15L AVR RISC microcontroller architecture. The AVR uses a Harvard
architecture concept with separate memories and buses for program and data memo-
ries. The program memory is accessed with a two-stage pipeline. While one instruction
is being executed, the next instruction is pre-fetched from the program memory. This
concept enables instructions to be executed in every clock cycle. The Program memory
is In-System Programmable Flash memory.
With the relative jump and relative call instructions, the whole address space is directly
accessed. All AVR instructions have a single 16-bit word format, meaning that every
program memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is
stored on the Stack. The Stack is a 3-level-deep Hardware Stack dedicated for subrou-
tines and interrupts.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, Timer/Counters and other I/O functions. The memory spaces in the AVR
architecture are all linear and regular memory maps.
512 x 16
Program
FLASH
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Direct Addressing
Status
and Test
Control
Registrers
Interrupt
Unit
2 x 8-bit
Timer/Counter
Watchdog
Timer
Analog
Comparator
I/O Lines
Data Bus 8-bit
SPI Unit
ADC
64 x 8
EEPROM