Rainbow Electronics ATtiny15L - Manual (Page 32)

32
ATtiny15L
1187E–AVR–06/02
Figure 22. Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A will read
the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A.
When OCR1A contains $00 or the top value, as specified in OCR1B Register, the output
PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is
shown in Table 13.
Timer/Counter1 Output
Compare RegisterB – OCR1B
The Output Compare Register1 (OCR1B) is an 8-bit read/write register. This register is
used in the PWM mode only, and it limits the top value to which the Timer/Counter1
keeps counting. After reaching OCR1B in PWM mode, the counter starts from $00.
In PWM mode, the Timer Overflow Flag (TOV1) is set as in normal Timer/Counter
mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode,
i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt and global
interrupts are enabled. This also applies to the Timer Output Compare A Flag and
interrupt.
PWM Output OC1A
PWM Output OC1A
Unsynchronized OC1A Latch
Synchronized OC1A Latch
Counter Value
Compare Value
Counter Value
Compare Value
Compare Value Changes
Glitch
Compare Value Changes
Bit 7 6 5 4 3 2 1 0
$2D MSB LSB OCR1B
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 1 1 1 1 1 1 1 1
Table 13. PWM Outputs when OCR1A = $00 or OCR1B
COM1A1 COM1A0 OCR1B Output PWMn
1 0 $00 L
1 0 OCR1B H
1 1 $00 H
1 1 OCR1B L