Rainbow Electronics ATtiny15L - Manual (Page 34)

34
ATtiny15L
1187E–AVR–06/02
The Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator that runs at 1 MHz.
This is the typical value at V
CC
= 5V. See “Typical Characteristics” on page 66 for typical
values at other V
CC
levels. By controlling the Watchdog Timer prescaler, the Watchdog
Reset interval can be adjusted from 16 to 2,048 ms, as shown in Table 15. The WDR
(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle
periods can be selected to determine the reset period. If the reset period expires without
another Watchdog Reset, the ATtiny15L resets and executes from the Reset Vector.
For timing details on the Watchdog Reset, refer to page 17.
To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be
followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 23. Watchdog Timer
The Watchdog Timer Control
Register – WDTCR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny15L and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared
(zero), the Watchdog Timer function is disabled. WDE can be cleared only when the
WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-
dure must be followed:
1 MHz at Vcc = 5V
350 KHz at Vcc = 3V WATCHDOG
PRESCALER
WATCHDOG
Oscillator
RESET
WDP0
WDP1
WDP2
WDE
MCU RESET
Bit 7 6 5 4 3 2 1 0
$21 – – – WDTOE WDE WDP2 WDP1 WDP0 WDTCR
Read/Write R R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0