Rainbow Electronics ATA6823 - Manual (Page 13)

13
4856E–AUTO–07/07
ATA6823 [Preliminary]
5.8 VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage
will be used as one input for the charge pump, which generates the gate voltage for the
high-side driver. The purpose of the regulator is to limit the gate voltage for the external power
MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage
is reduced if the supply voltage at VBAT falls below 12V.
5.9 Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transis-
tors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the
output voltage on the reservoir capacitor is V
BAT
plus VG. The charge pump is clocked with a
dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC
level.
5.10 Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning
level will be reached at 150°C. At this point the IC stays fully functional and a warning will be
sent to the microcontroller. At junction temperature 165°C the VCC regulator will be switched off
and a reset occurs.
5.11 H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side
drivers and two push-pull drivers for control of two external power NMOS used as low-side driv-
ers. The drivers are able to be used with standard and logic-level power NMOS.
The drivers for the high-side control use the charge pump voltage to supply the gates with a volt-
age of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is
possible to control the external load (motor) in the forward and reverse direction (see
Table 5-1
on page 12 ). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in
both directions.
5.11.1 Cross Conduction Time
To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the exter-
nal power NMOS is realized. An external RC combination defines the cross conduction time in
the following way:
t
CC
(µs) = 0.41
×
R
CC
(k
Ω
)
×
C
CC
(nF) (tolerance: ±5% ±0.15 µs)
The RC combination is charged to 5V and the switching level of the internal comparator is 67%
of the start level.
The resistor R
CC
must be greater than 5 k
Ω
and should be as close as possible to 10 k
Ω
, the C
CC
value has to be
≤
5 nF. Use of COG capacitor material is recommended.
The time measurement is triggered by the PWM or DIR signal crossing the 50% level.