Max8775 – Rainbow Electronics MAX8775 User Manual
Page 26
MAX8775
where I
IN
is the average input current:
In combined mode (REFIN2 = V
CC
) with both phases
active, the input RMS current simplifies to:
For most applications, nontantalum chemistries (ceram-
ic, aluminum, or OS-CON) are preferred due to their
resistance to power-up surge currents typical of sys-
tems with a mechanical switch or connector in series
with the input. Choose a capacitor that has less than
10°C temperature rise at the RMS input current for opti-
mal reliability and lifetime.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention.
The high-side MOSFET (N
H
) must be able to dissipate
the resistive losses plus the switching losses at both
V
IN(MIN)
and V
IN(MAX)
. Ideally, the losses at V
IN(MIN)
should be roughly equal to the losses at V
IN(MAX)
, with
lower losses in between. If the losses at V
IN(MIN)
are
significantly higher, consider increasing the size of N
H
.
Conversely, if the losses at V
IN(MAX)
are significantly
higher, consider reducing the size of N
H
. If V
IN
does
not vary over a wide range, optimum efficiency is
achieved by selecting a high-side MOSFET (N
H
) that
has conduction losses equal to the switching losses.
Choose a low-side MOSFET (N
L
) that has the lowest
possible on-resistance (R
DS(ON)
), comes in a moderate-
sized package (i.e., 8-pin SO, DPAK, or D
2
PAK), and is
reasonably priced. Ensure that the MAX8775 DL_ gate
driver can supply sufficient current to support the gate
charge and the current injected into the parasitic drain-
to-gate capacitor caused by the high-side MOSFET
turning on; otherwise, cross-conduction problems can
occur. Switching losses are not an issue for the low-side
MOSFET since it is a zero-voltage switched device
when used in the step-down topology.
Power-MOSFET Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (N
H
), the worst-
case power dissipation due to resistance occurs at
minimum input voltage:
PD (N
H
Resistive) =
Generally, use a small high-side MOSFET to reduce
switching losses at high input voltages. However, the
R
DS(ON)
required to stay within package power-dissi-
pation limits often limits how small the MOSFET can be.
The optimum occurs when the switching losses equal
the conduction (R
DS(ON)
) losses. High-side switching
losses do not become an issue until the input is greater
than approximately 15V.
Calculating the power dissipation in high-side MOSFETs
(N
H
) due to switching losses is difficult, since it must
allow for difficult-to-quantify factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PCB layout characteristics. The
following switching loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a ther-
mocouple mounted on N
H
:
PD (N
H
Switching) =
where C
RSS
is the reverse transfer capacitance of N
H
,
and I
GATE
is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become
a heat problem when maximum AC adapter voltages
are applied, due to the squared term in the switching-
loss equation (C x V
IN
2
x f
SW
). If the high-side MOSFET
chosen for adequate R
DS(ON)
at low battery voltages
becomes extraordinarily hot when subjected to
V
IN(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (N
L
), the worst-case power
dissipation always occurs at maximum battery voltage:
PD (N
L
Resistive) =
The absolute worst case for MOSFET power dissipation
occurs under heavy overload conditions that are
greater than I
LOAD(MAX)
, but are not high enough to
exceed the current limit and cause the fault latch to trip.
To protect against this possibility, “overdesign” the cir-
cuit to tolerate:
1
2
−
⎛
⎝⎜
⎞
⎠⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
(
)
V
V
I
R
OUT
IN MAX
LOAD
DS ON
(
)
(
)
(
)
(
)
(
)
V
I
f
I
Q
I
C
V
f
IN MAX LOAD SW
GATE
G SW
GATE
OSS IN MAX
SW
⎛
⎝⎜
⎞
⎠⎟
⎛
⎝⎜
⎞
⎠⎟
+
2
2
V
V
I
R
OUT
IN
LOAD
DS ON
⎛
⎝⎜
⎞
⎠⎟
(
)
2
(
)
I
I
V
V
V
V
RMS
OUT
OUT
IN
OUT
IN
=
⎛
⎝⎜
⎞
⎠⎟
−
⎛
⎝⎜
⎞
⎠⎟
1
2
I
V
V
I
V
V
I
IN
OUT
IN
OUT
OUT
IN
OUT
= ⎛
⎝⎜
⎞
⎠⎟
+ ⎛
⎝⎜
⎞
⎠⎟
1
1
2
2
Dual and Combinable Graphics Core
Controller for Notebook Computers
26
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