Rainbow Electronics MAX8775 - Manual (Page 21)

While ON2 is low, PGOOD2 is blanked high imped-
ance. When ON2 goes high again, the PGOOD2 cur-
rent-balance comparator is reenabled.
Current Balance (CCI2)
CCI2 is the output of the current-balance transconduc-
tance amplifier. The voltage level on CCI2 allows fine
adjustment to the duty cycle of phase 2, keeping phase
2’s current in balance with phase 1. When V
CCI2 is 20%
above or below V REF , PGOOD2 goes low, indicating
the currents in the two phases are not balanced.
Place a 47pF capacitor from CCI2 to AGND to integrate
the current balance error. CCI2 is clamped to REF
when ON2 is low.
CCI2 is unused in separate mode, and can be left
unconnected.
Current-Limit Protection
The current-limit circuit uses differential current-sense
inputs (CSH_ and CSL_) to limit the peak inductor cur-
rent. If the magnitude of the current-sense signal
exceeds the current-limit threshold, the PWM controller
turns off the high-side MOSFET (Figure 3). At the next
rising edge of the internal oscillator, the PWM controller
does not initiate a new cycle unless the current-sense
signal drops below the current-limit threshold. The
actual maximum load current is less than the peak cur-
rent-limit threshold by an amount equal to half the
inductor ripple current. Therefore, the maximum load
capability is a function of the current-sense resistance,
inductor value, switching frequency, and duty cycle
(V
OUT /V IN ).
In forced-PWM mode, the MAX8775 also implements a
negative current limit to prevent excessive reverse
inductor currents when V
OUT is sinking current. The
negative current-limit threshold is set to approximately
-120% of the positive current limit and tracks the posi-
tive current limit.
The current limit is fixed at 30mV (typ).
MOSFET Gate Drivers (DH_, DL_)
The DH_ and DL_ drivers are optimized for driving
moderate-sized high-side, and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V
IN -
V OUT differential exists. The high-side gate drivers
(DH_) source and sink 2A, and the low-side gate dri-
vers (DL_) source 1.7A and sink 3.3A. This ensures
robust gate drive for high-current applications. The
DH_ floating high-side MOSFET drivers are powered by
charge pumps at BST_ while the DL_ synchronous-rec-
tifier drivers are powered directly by the external 5V
supply (V
DD
).
Adaptive dead-time circuits monitor the DL_ and DH_
drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficien-
cy. There must be a low-resistance, low-inductance
path from the DL_ and DH_ drivers to the MOSFET
gates for the adaptive dead-time circuits to work prop-
erly; otherwise, the sense circuitry in the MAX8775
interprets the MOSFET gates as “off” while charge
actually remains. Use very short, wide traces (50 mils to
100 mils wide if the MOSFET is 1in from the driver).
The internal pulldown transistor that drives DL_ low is
robust, with a 0.6Ω (typ) on-resistance. This helps pre-
vent DL_ from being pulled up due to capacitive cou-
pling from the drain to the gate of the low-side MOSFETs
when the inductor node (LX_) quickly switches from
ground to V
IN . Applications with high input voltages and
long inductive driver traces may require additional gate-
to-source capacitance to ensure fast-rising LX_ edges,
do not pull up the low-side MOSFETs’ gate, causing
shoot-through currents. The capacitive coupling
between LX_ and DL_ created by the MOSFETs’ gate-to-
drain capacitance (C
RSS ), gate-to-source capacitance
(C ISS - C RSS ), and additional board parasitics should not
exceed the following minimum threshold:
Lot-to-lot variation of the threshold voltage can cause
problems in marginal designs. Adding a resistor less
than 10Ω in series with BST_ might remedy the problem
by increasing the turn-on time of the high-side MOSFET
without degrading the turn-off time.
Power-Good Output (PGOOD_)
PGOOD_ is the open-drain output of a comparator that
continuously monitors each SMPS output voltage for
overvoltage and undervoltage conditions. PGOOD_ is
actively held low in shutdown (ON_ = GND), soft-start,
and soft-shutdown. Once the soft-start terminates,
PGOOD_ becomes high impedance as long as the out-
put does not drop below 150mV from the nominal regu-
lation voltage set by REFIN_. PGOOD_ goes low once
the output drops 150mV below its nominal regulation
point, an output overvoltage fault occurs, or ON_ is
pulled low. For a logic-level PGOOD_ output voltage,
connect an external pullup resistor between PGOOD_
and +5V or +3.3V. A 100kΩ pullup resistor works well in
most applications.
PGOOD_ is blanked high impedance during all transi-
tions detected at REFIN_ until 20µs after the output
reaches the regulation voltage.
V V
C
C
GS TH IN
RSS
ISS
( )
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MAX8775
Dual and Combinable Graphics Core
Controller for Notebook Computers
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