2 watchdog timer during power down mode and idle – Rainbow Electronics T89C51AC2 User Manual

Page 67

T89C51AC2

Rev. B – 19-Dec-01

14.2 WatchDog Timer
during Power down
mode and Idle

In Power Down mode the oscillator stops, which means the WDT also stops. While in
Power Down mode, the user does not need to service the WDT. There are 2 methods of
exiting Power Down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power Down mode. When Power Down is exited with
hardware reset, the watchdog is disabled. Exiting Power Down with an interrupt is signif-
icantly different. The interrupt shall be held low long enough for the oscillator to stabilize.
When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service
for the interrupt used to exit Power Down.
To ensure that the WDT does not overflow within a few states of exiting powerdown, it is
best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting
T89C51AC2 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.

14.2.1 Register

Table 34. WDTPRG Register

WDTPRG (S:A7h)
WatchDog Timer Duration
Programming register

Reset Value = XXXX X000b

Bit

Number

Bit

Mnemonic

Description

Reserved
The value read from this bit is indeterminate. Do not set this bit.

WatchDog Timer Duration selection bit 2
Work in conjunction with bit 1 and bit 0.

WatchDog Timer Duration selection bit 1
Work in conjunction with bit 2 and bit 0.

WatchDog Timer Duration selection bit 0
Work in conjunction with bit 1 and bit 2.