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Applications information – Rainbow Electronics MAX17008 User Manual

Page 32

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MAX17007A/MAX17008

Dual and Combinable QPWM Graphics
Core Controllers for Notebook Computers

32

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Calculating the power dissipation in high-side MOSFET
(N

H

) due to switching losses is difficult since it must

allow for difficult quantifying factors that influence the
turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage,
source inductance, and PCB layout characteristics. The
following switching-loss calculation provides only a very
rough estimate and is no substitute for breadboard
evaluation, preferably including verification using a
thermocouple mounted on N

H

:

where C

OSS

is the N

H

MOSFET’s output capacitance,

Q

G(SW)

is the charge needed to turn on the N

H

MOS-

FET, and I

GATE

is the peak gate-drive source/sink cur-

rent (2.4A typ).

Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the C x
V

IN

2

x f

SW

switching-loss equation. If the high-side

MOSFET chosen for adequate R

DS(ON)

at low battery

voltages becomes extraordinarily hot when biased from
V

IN(MAX)

, consider choosing another MOSFET with

lower parasitic capacitance.

For the low-side MOSFET (N

L

), the worst-case power

dissipation always occurs at maximum input voltage:

The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I

LOAD(MAX)

, but are not quite high enough to exceed

the current limit and cause the fault latch to trip. To pro-
tect against this possibility, you can “over design” the
circuit to tolerate:

where I

VALLEY(MAX)

is the maximum valley current

allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good size heatsink to handle the overload
power dissipation.

Choose a Schottky diode (D

L

) with a forward voltage

low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current during the dead
times. This diode is optional and can be removed if effi-
ciency is not critical.

Boost Capacitors

The boost capacitors (C

BST

) must be selected large

enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1μF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current appli-
cations driving large, high-side MOSFETs require boost
capacitors larger than 0.1μF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the high-
side MOSFETs’ gates:

where N is the number of high-side MOSFETs used for
one regulator, and Q

GATE

is the gate charge specified

in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a sin-
gle IRF7811W has a maximum gate charge of 24nC
(V

GS

= 5V). Using the above equation, the required

boost capacitance would be:

Selecting the closest standard value, this example
requires a 0.22μF ceramic capacitor.

Applications Information

Minimum Input Voltage Requirements

and Dropout Performance

The output-voltage adjustable range for continuous-
conduction operation is restricted by the nonadjustable
minimum off-time one-shot. For best dropout perfor-
mance, use the slower (200kHz) on-time settings. When
working with low input voltages, the duty-factor limit
must be calculated using worst-case values for on- and
off-times. Manufacturing tolerances and internal propa-
gation delays introduce an error to the on-times. This
error is greater at higher frequencies. Also, keep in
mind that transient response performance of buck reg-
ulators operated too close to dropout is poor, and bulk
output capacitance must often be added (see the

Transient Response

section (the V

SAG

equation) in the

Quick-PWM Design Procedure

section).

C

nC

mV

μF

BST

= ×

=

2

24

200

0 24

.

C

N Q

mV

BST

GATE

= ×

200

I

I

I

I

I

LIR

LOAD

VALLEY MAX

INDUCTOR

VALLEY MAX

LOAD MAX

=

+


⎝⎜


⎠⎟

=

+


⎝⎜


⎠⎟

(

)

(

)

(

)

Δ

2

2

PD NL

sistive

V

V

I

R

OUT

IN MAX

LOAD

DS ON

(

Re

)

(

)

(

)

= −



(

)

1

2

PD NHSwitching

V

I

f

Q

I

IN MAX LOAD SW

G SW

GATE

(

)

(

)

(

)

=

⎛⎛


+

C

OSS

V

V

f

IN MAX

SW

(

)

2

2