American Magnetics 187 Self-Compensating Liquid Level Controller - Manual (Page 53)

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Remote Interface Reference
Status System Commands
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*ESE < enable_value >
Enables bits in the Standard Event register to be reported in the
“Standard Event” bit (bit 5) of the Status Byte register. To enable bits, you
must write a decimal
< enable_value > which corresponds to the binary-
weighted sum of the bits you wish to enable. Refer to Table 4-2 on page 35
for more information. For example, to enable all categories of error
messages to be reported in bit 5 of the Status Byte register, send:
*ESE 60;
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*ESE?
The *ESE? query returns a decimal sum which corresponds to the binary-
weighted sum of the bits enabled by the last *ESE command.
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*PSC {0|1}
Power-On Status Clear. If *PSC 1 is in effect, the Standard Event enable
register and the Status Byte enable register are cleared at power on. If
*PSC 0 is in effect, the enable registers are not cleared at power on. The
default setting is “1”.
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*PSC?
Returns the Power-On Status Clear setting currently in effect. A value of
“0” indicates the enable registers are not cleared at power on; a value of “1”
indicates the enable registers are cleared at power on.
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*OPC
Sets the “Operation Complete” bit (bit 0) of the Standard Event register
when executed. See page 37 for a complete discussion.
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*OPC?
Returns “1” to the requesting interface when executed. See page 37 for
more information.
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STATus:ALARm:CONDition?
Returns the contents of the Alarm Condition register as a binary-weighted
sum.
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STATus:ALARm:EVENt?
Returns the contents of the Alarm Event register as a binary-weighted
sum.
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STATus:ALARm:ENABle < enable_value >
Enables bits in the Alarm Event register to be reported in the “Alarm
Event” bit (bit 2) of the Status Byte register. To enable bits, you must
write a decimal
< enable_value > which corresponds to the binary-weighted