American Magnetics 187 Self-Compensating Liquid Level Controller - Manual (Page 43)

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Remote Interface Reference
SCPI Status System
enable register. To enable or disable bits in an enable register, write a
decimal value which corresponds to the binary-weighted sum of the bits
you wish reported to the Status Byte register.
4.2.2.1 Status Byte Registers
The Status Byte register group reports conditions from the Standard
Event register or output buffers. Data in the output buffer is immediately
reported in the “IEEE-488 Message Available” bit (bit 4) or the “Serial
Message Available” bit (bit 3). Clearing a bit in the Standard Event or
Alarm Event registers will update the corresponding bit in the Status Byte
register, according to the Standard Event and Alarm Event enable
registers. Reading the pending messages in the output buffers will clear
the appropriate “Message Available” bit. The bit definitions for the Status
Byte register are defined in Table 4-1.
The Status Byte register provides the capability of generating a user-
defined IEEE-488 service request (SRQ) by enabling the desired bits using
the
*SRE < value > command. If a Status Byte register bit is enabled, then
when that bit is set, an SRQ is generated on the IEEE-488 bus. For
example, if the command
*SRE 2 is sent to the Model 187, then if the
controller output is energized, the Model 187 will immediately generate an
SRQ on the IEEE-488 bus.
Table 4-1. Bit definitions for the Status Byte register.
Bit Number
Decimal
Value Definition
0 Fill Expired 1 “1” indicates the fill timeout period
has expired.
1 Fill State 2 “1” indicates the controller output is
energized. “0” indicates the output is
de-energized.
2 Alarm Event 4 One or more enabled bits are set in
the Alarm Event register.
3 Serial Message
Available
8 The serial output buffer contains
unread data.
4 IEEE-488 Message
Available
16 The IEEE-488 output buffer contains
unread data.
5 Standard Event 32 One or more enabled bits are set in
the Standard Event register.
6 Status Byte
Summary
64 One or more enabled bits are set in
the Status Byte register.
7 Not Used 128 Always “0”.