Texas Instruments TMS320DM644x - Manual (Page 5)

List of Tables
1 GPIO Register Bits and Banks Associated With GPIO Pins ......................................................... 10
2 GPIO Interrupts to the ARM CPU and DSP CPU ...................................................................... 13
3 GPIO Synchronization Events to the EDMA
............................................................................
15
4 General-Purpose Input/Output (GPIO) Registers
......................................................................
16
5 Peripheral Identification Register (PID) Field Descriptions ........................................................... 17
6 GPIO Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions ........................................... 18
7 GPIO Direction Register (DIRn) Field Descriptions
....................................................................
19
8 GPIO Output Data Register (OUT_DATAn) Field Descriptions ...................................................... 20
9 GPIO Set Data Register (SET_DATAn) Field Descriptions .......................................................... 22
10 GPIO Clear Data Register (CLR_DATAn) Field Descriptions ........................................................ 24
11 GPIO Input Data Register (IN_DATAn) Field Descriptions
...........................................................
25
12 GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIGn) Field Descriptions ................................. 27
13 GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) Field Descriptions ............................... 29
14 GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIGn) Field Descriptions ................................. 31
15 GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn) Field Descriptions
..............................
33
16 GPIO Interrupt Status Register (INTSTATn) Field Descriptions ..................................................... 35
SPRUE25 – December 2005 List of Tables 5