Texas Instruments TMS320DM644x - Manual (Page 3)

Contents
Preface ............................................................................................................................... 6
1 Introduction ................................................................................................................ 8
1.1 Purpose of the Peripheral .......................................................................................... 8
1.2 Features .............................................................................................................. 8
1.3 Functional Block Diagram
.........................................................................................
9
1.4 Industry Standard(s) Compliance Statement
....................................................................
9
2 Peripheral Architecture ................................................................................................ 9
2.1 Clock Control
........................................................................................................
9
2.2 Signal Descriptions ................................................................................................. 9
2.3 GPIO Register Structure ......................................................................................... 10
2.4 Using a GPIO Signal as an Output ............................................................................. 11
2.5 Using a GPIO Signal as an Input
...............................................................................
12
2.6 Reset Considerations
.............................................................................................
13
2.7 Interrupt Support .................................................................................................. 13
2.8 EDMA Event Support ............................................................................................. 15
2.9 Power Management ............................................................................................... 15
2.10 Emulation Considerations
........................................................................................
15
3 Registers .................................................................................................................. 16
3.1 Peripheral Identification Register (PID)
.........................................................................
17
3.2 GPIO Interrupt Per-Bank Enable Register (BINTEN)
.........................................................
18
3.3 GPIO Direction Registers (DIRn) ................................................................................ 19
3.4 GPIO Output Data Register (OUT_DATAn) ................................................................... 20
3.5 GPIO Set Data Register (SET_DATAn) ........................................................................ 21
3.6 GPIO Clear Data Register (CLR_DATAn)
.....................................................................
23
3.7 GPIO Input Data Register (IN_DATAn)
........................................................................
25
3.8 GPIO Set Rising Edge Interrupt Register (SET_RIS_TRIGn) ............................................... 26
3.9 GPIO Clear Rising Edge Interrupt Register (CLR_RIS_TRIGn) ............................................ 28
3.10 GPIO Set Falling Edge Interrupt Register (SET_FAL_TRIGn) .............................................. 30
3.11 GPIO Clear Falling Edge Interrupt Register (CLR_FAL_TRIGn)
..........................................
32
3.12 GPIO Interrupt Status Register (INTSTATn)
...................................................................
34
SPRUE25 – December 2005 Table of Contents 3